Another IEEE paper

[ipdf/documents.git] / LiteratureNotes.tex

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@@ -477,6 +477,30 @@ Using unix domain sockets we can execute the FPU as a child process and communic
 
 Using \shell{ghdl} the testbench can also be linked as part a C/C++ program and run using a function; however there is still no way to communicate with it other than forking a child process and using a unix domain socket anyway. Also, compiling the VHDL FPU as part of our document viewer would clutter the code repository and probably be highly unportable. The VHDL FPU has been given a seperate repository.
 
+\section{On the design of fast IEEE floating-point adders\cite{seidel2001onthe}}
+
+This paper gives an overview of the ``Naive'' floating point addition/subtraction algorithm and gives several optimisation techniques:
+
+TODO: Actually understand these...
+
+\begin{itemize}
+       \item Use parallel paths (based on exponent)
+       \item Unification of significand result ranges
+       \item Reduction of IEEE rounding modes
+       \item Sign-magnitude computation of a difference
+       \item Compound Addition
+       \item Approximate counting of leading zeroes
+       \item Pre-computation of post-normalization shift
+\end{itemize}
+
+They then give an implementation that uses these optimisation techniques including very scary looking block diagrams.
+
+They simulated the FPU. Does not mention what simulation method was used directly, but cites another paper (TODO: Look at this. I bet it was VHDL).
+
+The paper concludes by summarising the optimisation techniques used by various adders in production (in 2001).
+
+This paper does not specifically mention the precision of the operations, but may be useful because a faster adder design might mean you can increase the precision.
+
 
 % Back to software
 \section{Basic Issues in Floating Point Arithmetic and Error Analysis\cite{demmel1996basic}}