Another IEEE paper

[ipdf/documents.git] / papers.bib

diff --git a/papers.bib b/papers.bib
index 2c75525..0dec3ca 100644 (file)
--- a/papers.bib
+++ b/papers.bib
@@ -490,6 +490,29 @@ doi={10.1109/ARITH.1991.145549},}
        howpublished = "\url{http://ghdl.free.fr/ghdl/}"
 }
 
+% Look into as an alternative to using text files for FPU simulation?
+@misc{tang2000using,
+       title = "Using Binary Files in VHDL Test Benches",
+       author = "Stephen Tang",
+       year = "2000",
+       howpublished = "\url{http://www.ece.ualberta.ca/~elliott/ee552/studentAppNotes/2000_w/vhdl/BinaryFileTestbenching/binary.html}",
+       note = "Application Notes (webpage)"
+}
+
+% On the design of IEEE floating point adders
+% Has algorithms!
+@INPROCEEDINGS{seidal2001onthe,
+author={Seidel, P.-M. and Even, G.},
+booktitle={Computer Arithmetic, 2001. Proceedings. 15th IEEE Symposium on},
+title={On the design of fast IEEE floating-point adders},
+year={2001},
+month={},
+pages={184-194},
+keywords={adders;circuit optimisation;floating point arithmetic;logic design;IEEE rounding modes;IEEE standard;addition;approximate counting;borrow-save representation;clock periods;complement subtraction;compound adders;double precision;fast IEEE floating-point adder design;fast circuits;latches;latency;leading zeros;logic levels;normalized numbers;normalized rounded sum/difference;optimization techniques;rounding algorithm;sign-magnitude computation;subtraction;Adders;Algorithm design and analysis;Circuits;Clocks;Delay;Design optimization;Latches;Logic design;Partitioning algorithms;Pipelines},
+doi={10.1109/ARITH.2001.930118},
+ISSN={1063-6889},}
+
+
 @article{demmel1996basic,
        title = "Basic Issues in Floating Point Arithmetic and Error Analysis",
        author = "Jim Demmel",
@@ -503,3 +526,5 @@ doi={10.1109/ARITH.1991.145549},}
        author = "Edvin Catovic",
        howpublished = "\url{http://www.gaisler.com/doc/grfpu_dasia.pdf}"
 }
+
+