Tidy File I/O in mainloop

Tidy File I/O in mainloop

I tried really hard to do binary file I/O but failed.

Guess how VHDL represents a file of "bits"?
As an ASCII text file of "0" or "1" (!)

So looks like ASCII string -> hex -> std_logic_vector is best we can do.
I guess what people don't know won't hurt them... much.

Fixed some mistakes, mainloop was still trying to read the comparison output, also I called the file "input_file"
and there was a variable called "input" still that was getting read -_-