Specifically, remove the magic 8 bit exponent / 23 bit mantissa (32 bit IEEE) numbers.
There are *a lot* of them. A lot are still there.
=> Don't run this vfpu it is probably broken.
At the very least do not change any of the constants in fpupack.vhd
-------------------------------------------------------------------------------
---
--- Project: <Floating Point Unit Core>
---
-- Description: component package
--------------------------------------------------------------------------------
---
--- 100101011010011100100
--- 110000111011100100000
--- 100000111011000101101
--- 100010111100101111001
--- 110000111011101101001
--- 010000001011101001010
--- 110100111001001100001
--- 110111010000001100111
--- 110110111110001011101
--- 101110110010111101000
--- 100000010111000000000
---
--- Author: Jidan Al-eryani
---
--- Copyright (C) 2006
---
--- This source file may be used and distributed without
--- restriction provided that this copyright statement is not
--- removed from the file and that any derivative work contains
--- the original copyright notice and the associated disclaimer.
---
--- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
--- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
--- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
--- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
--- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
--- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
--- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
--- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
--- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
+-- See COPYRIGHT.jop
library ieee;
use ieee.std_logic_1164.all;
package comppack is
+--- NOTE: I have kept the original naming convention (ie: The names include the number of bits if we were using single precision IEEE floats)
+
+--- Constants --- -- carry(1) & hidden(1) & fraction(FRAC_WIDTH) & guard(1) & round(1) & sticky(1)
+constant FRAC_COMP_WIDTH : integer := 1 + 1 + FRAC_WIDTH + 1 + 1 + 1;
--- Component Declartions ---
component pre_norm_addsub is
port(clk_i : in std_logic;
- opa_i : in std_logic_vector(31 downto 0);
- opb_i : in std_logic_vector(31 downto 0);
- fracta_28_o : out std_logic_vector(27 downto 0); -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
- fractb_28_o : out std_logic_vector(27 downto 0);
- exp_o : out std_logic_vector(7 downto 0));
+ opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
+ opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
+
+ fracta_28_o : out std_logic_vector(FRAC_COMP_WIDTH-1 downto 0);
+ fractb_28_o : out std_logic_vector(FRAC_COMP_WIDTH-1 downto 0);
+ exp_o : out std_logic_vector(EXP_WIDTH-1 downto 0));
end component;
component addsub_28 is
port(clk_i : in std_logic;
fpu_op_i : in std_logic;
- fracta_i : in std_logic_vector(27 downto 0); -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
- fractb_i : in std_logic_vector(27 downto 0);
+ fracta_i : in std_logic_vector(FRAC_COMP_WIDTH-1 downto 0); -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
+ fractb_i : in std_logic_vector(FRAC_COMP_WIDTH-1 downto 0);
signa_i : in std_logic;
signb_i : in std_logic;
- fract_o : out std_logic_vector(27 downto 0);
+ fract_o : out std_logic_vector(FRAC_COMP_WIDTH-1 downto 0);
sign_o : out std_logic);
end component;
component post_norm_addsub is
port(clk_i : in std_logic;
- opa_i : in std_logic_vector(31 downto 0);
- opb_i : in std_logic_vector(31 downto 0);
- fract_28_i : in std_logic_vector(27 downto 0); -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
- exp_i : in std_logic_vector(7 downto 0);
+ opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
+ opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
+ fract_28_i : in std_logic_vector(FRAC_COMP_WIDTH-1 downto 0); -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
+ exp_i : in std_logic_vector(EXP_WIDTH-1 downto 0);
sign_i : in std_logic;
fpu_op_i : in std_logic;
rmode_i : in std_logic_vector(1 downto 0);
- output_o : out std_logic_vector(31 downto 0);
+ output_o : out std_logic_vector(FP_WIDTH-1 downto 0);
ine_o : out std_logic
);
end component;
component pre_norm_mul is
port(
clk_i : in std_logic;
- opa_i : in std_logic_vector(31 downto 0);
- opb_i : in std_logic_vector(31 downto 0);
+ opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
+ opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
exp_10_o : out std_logic_vector(9 downto 0);
- fracta_24_o : out std_logic_vector(23 downto 0); -- hidden(1) & fraction(23)
- fractb_24_o : out std_logic_vector(23 downto 0)
+ fracta_24_o : out std_logic_vector(FRAC_WIDTH downto 0); -- hidden(1) & fraction(23)
+ fractb_24_o : out std_logic_vector(FRAC_WIDTH downto 0)
);
end component;
component mul_24 is
port(
clk_i : in std_logic;
- fracta_i : in std_logic_vector(23 downto 0); -- hidden(1) & fraction(23)
- fractb_i : in std_logic_vector(23 downto 0);
+ fracta_i : in std_logic_vector(FRAC_WIDTH downto 0); -- hidden(1) & fraction(23)
+ fractb_i : in std_logic_vector(FRAC_WIDTH downto 0);
signa_i : in std_logic;
signb_i : in std_logic;
start_i : in std_logic;
- fract_o : out std_logic_vector(47 downto 0);
+ fract_o : out std_logic_vector(2*FRAC_WIDTH+1 downto 0);
sign_o : out std_logic;
ready_o : out std_logic
);
component post_norm_mul is
port(
clk_i : in std_logic;
- opa_i : in std_logic_vector(31 downto 0);
- opb_i : in std_logic_vector(31 downto 0);
+ opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
+ opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
exp_10_i : in std_logic_vector(9 downto 0);
- fract_48_i : in std_logic_vector(47 downto 0); -- hidden(1) & fraction(23)
+ fract_48_i : in std_logic_vector(2*FRAC_WIDTH+1 downto 0); -- hidden(1) & fraction(23)
sign_i : in std_logic;
rmode_i : in std_logic_vector(1 downto 0);
- output_o : out std_logic_vector(31 downto 0);
+ output_o : out std_logic_vector(FP_WIDTH-1 downto 0);
ine_o : out std_logic
);
end component;
component pre_norm_sqrt is
port(
clk_i : in std_logic;
- opa_i : in std_logic_vector(31 downto 0);
- fracta_52_o : out std_logic_vector(51 downto 0);
- exp_o : out std_logic_vector(7 downto 0));
+ opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
+ fracta_52_o : out std_logic_vector(2*(FRAC_COMP_WIDTH-2)-1 downto 0);
+ exp_o : out std_logic_vector(EXP_WIDTH-1 downto 0));
end component;
component sqrt is
component post_norm_sqrt is
port( clk_i : in std_logic;
- opa_i : in std_logic_vector(31 downto 0);
- fract_26_i : in std_logic_vector(25 downto 0); -- hidden(1) & fraction(11)
- exp_i : in std_logic_vector(7 downto 0);
+ opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
+ fract_26_i : in std_logic_vector(FRAC_WIDTH+2 downto 0); -- hidden(1) & fraction(11)
+ exp_i : in std_logic_vector(EXP_WIDTH-1 downto 0);
ine_i : in std_logic;
rmode_i : in std_logic_vector(1 downto 0);
- output_o : out std_logic_vector(31 downto 0);
+ output_o : out std_logic_vector(FP_WIDTH-1 downto 0);
ine_o : out std_logic);
end component;
-end comppack;
\ No newline at end of file
+end comppack;
--------------------------------------------------------------------------------
---
--- Project: <Floating Point Unit Core>
---
+-------------------------------------------------------------------------------
-- Description: top entity
--------------------------------------------------------------------------------
---
--- 100101011010011100100
--- 110000111011100100000
--- 100000111011000101101
--- 100010111100101111001
--- 110000111011101101001
--- 010000001011101001010
--- 110100111001001100001
--- 110111010000001100111
--- 110110111110001011101
--- 101110110010111101000
--- 100000010111000000000
---
--- Author: Jidan Al-eryani
---
--- Copyright (C) 2006
---
--- This source file may be used and distributed without
--- restriction provided that this copyright statement is not
--- removed from the file and that any derivative work contains
--- the original copyright notice and the associated disclaimer.
---
--- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
--- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
--- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
--- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
--- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
--- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
--- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
--- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
--- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
+-- See COPYRIGHT.jop
library ieee;
-- ***Add/Substract units signals***
- signal prenorm_addsub_fracta_28_o, prenorm_addsub_fractb_28_o : std_logic_vector(27 downto 0);
- signal prenorm_addsub_exp_o : std_logic_vector(7 downto 0);
+ signal prenorm_addsub_fracta_28_o, prenorm_addsub_fractb_28_o : std_logic_vector(FRAC_COMP_WIDTH-1 downto 0);
+ signal prenorm_addsub_exp_o : std_logic_vector(EXP_WIDTH-1 downto 0);
- signal addsub_fract_o : std_logic_vector(27 downto 0);
+ signal addsub_fract_o : std_logic_vector(FRAC_COMP_WIDTH-1 downto 0);
signal addsub_sign_o : std_logic;
- signal postnorm_addsub_output_o : std_logic_vector(31 downto 0);
+ signal postnorm_addsub_output_o : std_logic_vector(FP_WIDTH-1 downto 0);
signal postnorm_addsub_ine_o : std_logic;
-- ***Multiply units signals***
signal pre_norm_mul_exp_10 : std_logic_vector(9 downto 0);
- signal pre_norm_mul_fracta_24 : std_logic_vector(23 downto 0);
- signal pre_norm_mul_fractb_24 : std_logic_vector(23 downto 0);
+ signal pre_norm_mul_fracta_24 : std_logic_vector(FRAC_WIDTH downto 0);
+ signal pre_norm_mul_fractb_24 : std_logic_vector(FRAC_WIDTH downto 0);
- signal mul_24_fract_48 : std_logic_vector(47 downto 0);
+ signal mul_24_fract_48 : std_logic_vector(2*FRAC_WIDTH+1 downto 0);
signal mul_24_sign : std_logic;
- signal serial_mul_fract_48 : std_logic_vector(47 downto 0);
+ signal serial_mul_fract_48 : std_logic_vector(2*FRAC_WIDTH+1 downto 0);
signal serial_mul_sign : std_logic;
- signal mul_fract_48: std_logic_vector(47 downto 0);
+ signal mul_fract_48: std_logic_vector(2*FRAC_WIDTH+1 downto 0);
signal mul_sign: std_logic;
- signal post_norm_mul_output : std_logic_vector(31 downto 0);
+ signal post_norm_mul_output : std_logic_vector(FP_WIDTH-1 downto 0);
signal post_norm_mul_ine : std_logic;
-- ***Division units signals***
signal pre_norm_div_dvdnd : std_logic_vector(49 downto 0);
- signal pre_norm_div_dvsor : std_logic_vector(26 downto 0);
+ signal pre_norm_div_dvsor : std_logic_vector(FRAC_WIDTH+3 downto 0);
signal pre_norm_div_exp : std_logic_vector(EXP_WIDTH+1 downto 0);
- signal serial_div_qutnt : std_logic_vector(26 downto 0);
- signal serial_div_rmndr : std_logic_vector(26 downto 0);
+ signal serial_div_qutnt : std_logic_vector(FRAC_WIDTH+3 downto 0);
+ signal serial_div_rmndr : std_logic_vector(FRAC_WIDTH+3 downto 0);
signal serial_div_sign : std_logic;
signal serial_div_div_zero : std_logic;
- signal post_norm_div_output : std_logic_vector(31 downto 0);
+ signal post_norm_div_output : std_logic_vector(FP_WIDTH-1 downto 0);
signal post_norm_div_ine : std_logic;
-- ***Square units***
- signal pre_norm_sqrt_fracta_o : std_logic_vector(51 downto 0);
+ signal pre_norm_sqrt_fracta_o : std_logic_vector(2*(FRAC_COMP_WIDTH-2)-1 downto 0);
signal pre_norm_sqrt_exp_o : std_logic_vector(7 downto 0);
- signal sqrt_sqr_o : std_logic_vector(25 downto 0);
+ signal sqrt_sqr_o : std_logic_vector(FRAC_WIDTH+2 downto 0);
signal sqrt_ine_o : std_logic;
- signal post_norm_sqrt_output : std_logic_vector(31 downto 0);
+ signal post_norm_sqrt_output : std_logic_vector(FP_WIDTH-1 downto 0);
signal post_norm_sqrt_ine_o : std_logic;
fpu_op_i => s_fpu_op_i(0),
fracta_i => prenorm_addsub_fracta_28_o,
fractb_i => prenorm_addsub_fractb_28_o,
- signa_i => s_opa_i(31),
- signb_i => s_opb_i(31),
+ signa_i => s_opa_i(FP_WIDTH-1),
+ signb_i => s_opb_i(FP_WIDTH-1),
fract_o => addsub_fract_o,
sign_o => addsub_sign_o);
clk_i => clk_i,
fracta_i => pre_norm_mul_fracta_24,
fractb_i => pre_norm_mul_fractb_24,
- signa_i => s_opa_i(31),
- signb_i => s_opb_i(31),
+ signa_i => s_opa_i(FP_WIDTH-1),
+ signb_i => s_opb_i(FP_WIDTH-1),
start_i => start_i,
fract_o => mul_24_fract_48,
sign_o => mul_24_sign,
clk_i => clk_i,
fracta_i => pre_norm_mul_fracta_24,
fractb_i => pre_norm_mul_fractb_24,
- signa_i => s_opa_i(31),
- signb_i => s_opb_i(31),
+ signa_i => s_opa_i(FP_WIDTH-1),
+ signb_i => s_opb_i(FP_WIDTH-1),
start_i => s_start_i,
fract_o => serial_mul_fract_48,
sign_o => serial_mul_sign,
clk_i=> clk_i,
dvdnd_i => pre_norm_div_dvdnd,
dvsor_i => pre_norm_div_dvsor,
- sign_dvd_i => s_opa_i(31),
- sign_div_i => s_opb_i(31),
+ sign_dvd_i => s_opa_i(FP_WIDTH-1),
+ sign_div_i => s_opb_i(FP_WIDTH-1),
start_i => s_start_i,
ready_o => open,
qutnt_o => serial_div_qutnt,
end process;
- s_infa <= '1' when s_opa_i(30 downto 23)="11111111" else '0';
- s_infb <= '1' when s_opb_i(30 downto 23)="11111111" else '0';
+ s_infa <= '1' when s_opa_i(FP_WIDTH-2 downto FRAC_WIDTH)= (FP_WIDTH-2 downto FRAC_WIDTH => '1') else '0';
+ s_infb <= '1' when s_opb_i(FP_WIDTH-2 downto FRAC_WIDTH)= (FP_WIDTH-2 downto FRAC_WIDTH => '1') else '0';
--In round down: the subtraction of two equal numbers other than zero are always -0!!!
begin
if s_rmode_i="00" or (s_div_zero_o or (s_infa or s_infb) or s_qnan_o or s_snan_o)='1' then --round-to-nearest-even
s_output_o <= s_output1;
- elsif s_rmode_i="01" and s_output1(30 downto 23)="11111111" then
+ elsif s_rmode_i="01" and s_output1(FP_WIDTH-2 downto FRAC_WIDTH)="11111111" then
--In round-to-zero: the sum of two non-infinity operands is never infinity,even if an overflow occures
- s_output_o <= s_output1(31) & "1111111011111111111111111111111";
- elsif s_rmode_i="10" and s_output1(31 downto 23)="111111111" then
+ s_output_o <= s_output1(FP_WIDTH-1) & "1111111011111111111111111111111";
+ elsif s_rmode_i="10" and s_output1(FP_WIDTH-1 downto FRAC_WIDTH)="111111111" then
--In round-up: the sum of two non-infinity operands is never negative infinity,even if an overflow occures
s_output_o <= "11111111011111111111111111111111";
elsif s_rmode_i="11" then
--In round-down: a-a= -0
- if (s_fpu_op_i="000" or s_fpu_op_i="001") and s_zero_o='1' and (s_opa_i(31) or (s_fpu_op_i(0) xor s_opb_i(31)))='1' then
- s_output_o <= "1" & s_output1(30 downto 0);
+ if (s_fpu_op_i="000" or s_fpu_op_i="001") and s_zero_o='1' and (s_opa_i(FP_WIDTH-1) or (s_fpu_op_i(0) xor s_opb_i(FP_WIDTH-1)))='1' then
+ s_output_o <= "1" & s_output1(FP_WIDTH-2 downto 0);
--In round-down: the sum of two non-infinity operands is never postive infinity,even if an overflow occures
- elsif s_output1(31 downto 23)="011111111" then
+ elsif s_output1(FP_WIDTH-1 downto FRAC_WIDTH)="011111111" then
s_output_o <= "01111111011111111111111111111111";
else
s_output_o <= s_output1;
-- Generate Exceptions
- s_underflow_o <= '1' when s_output1(30 downto 23)="00000000" and s_ine_o='1' else '0';
- s_overflow_o <= '1' when s_output1(30 downto 23)="11111111" and s_ine_o='1' else '0';
+ s_underflow_o <= '1' when s_output1(FP_WIDTH-2 downto FRAC_WIDTH)="00000000" and s_ine_o='1' else '0';
+ s_overflow_o <= '1' when s_output1(FP_WIDTH-2 downto FRAC_WIDTH)="11111111" and s_ine_o='1' else '0';
s_div_zero_o <= serial_div_div_zero when fpu_op_i="011" else '0';
- s_inf_o <= '1' when s_output1(30 downto 23)="11111111" and (s_qnan_o or s_snan_o)='0' else '0';
- s_zero_o <= '1' when or_reduce(s_output1(30 downto 0))='0' else '0';
- s_qnan_o <= '1' when s_output1(30 downto 0)=QNAN else '0';
- s_snan_o <= '1' when s_opa_i(30 downto 0)=SNAN or s_opb_i(30 downto 0)=SNAN else '0';
+ s_inf_o <= '1' when s_output1(FP_WIDTH-2 downto FRAC_WIDTH)="11111111" and (s_qnan_o or s_snan_o)='0' else '0';
+ s_zero_o <= '1' when or_reduce(s_output1(FP_WIDTH-2 downto 0))='0' else '0';
+ s_qnan_o <= '1' when s_output1(FP_WIDTH-2 downto 0)=QNAN else '0';
+ s_snan_o <= '1' when s_opa_i(FP_WIDTH-2 downto 0)=SNAN or s_opb_i(FP_WIDTH-2 downto 0)=SNAN else '0';
end rtl;
--------------------------------------------------------------------------------
---
--- Project: <Floating Point Unit Core>
---
+
-- Description: FPU package wich contains constants and functions needed in the FPU core
--------------------------------------------------------------------------------
---
--- 100101011010011100100
--- 110000111011100100000
--- 100000111011000101101
--- 100010111100101111001
--- 110000111011101101001
--- 010000001011101001010
--- 110100111001001100001
--- 110111010000001100111
--- 110110111110001011101
--- 101110110010111101000
--- 100000010111000000000
---
--- Author: Jidan Al-eryani
---
--- Copyright (C) 2006
---
--- This source file may be used and distributed without
--- restriction provided that this copyright statement is not
--- removed from the file and that any derivative work contains
--- the original copyright notice and the associated disclaimer.
---
--- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
--- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
--- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
--- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
--- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
--- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
--- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
--- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
--- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
+-- See Copyright.jop
+
library ieee;
use ieee.std_logic_1164.all;
constant EXP_WIDTH : integer := 8;
--Zero vector
- constant ZERO_VECTOR: std_logic_vector(30 downto 0) := "0000000000000000000000000000000";
+ constant ZERO_VECTOR: std_logic_vector(FP_WIDTH-2 downto 0) := (others => '0');
-- Infinty FP format
- constant INF : std_logic_vector(30 downto 0) := "1111111100000000000000000000000";
+ constant INF : std_logic_vector(FP_WIDTH-2 downto 0) := (FP_WIDTH-2 downto FP_WIDTH-2-EXP_WIDTH+1 => '1', others => '0');
-- QNaN (Quit Not a Number) FP format (without sign bit)
- constant QNAN : std_logic_vector(30 downto 0) := "1111111110000000000000000000000";
+ constant QNAN : std_logic_vector(FP_WIDTH-2 downto 0) := (FP_WIDTH-2 downto FP_WIDTH-2-EXP_WIDTH => '1', others => '0');
-- SNaN (Signaling Not a Number) FP format (without sign bit)
- constant SNAN : std_logic_vector(30 downto 0) := "1111111100000000000000000000001";
+ constant SNAN : std_logic_vector(FP_WIDTH-2 downto 0) := (FP_WIDTH-2 downto FP_WIDTH-2-EXP_WIDTH+1 => '1', 0 => '1', others => '0');
-- count the zeros starting from left
function count_l_zeros (signal s_vector: std_logic_vector) return std_logic_vector;
-end fpupack;
\ No newline at end of file
+end fpupack;
use std.textio.all;
use work.txt_util.all;
+use work.fpupack.all;
+
-- fpu operations (fpu_op_i):
-- ========================
-- 000 = add,
);
end component;
-
+-- Assigning default values doesn't seem to help the error messages :(
signal clk_i : std_logic:= '1';
-signal opa_i, opb_i : std_logic_vector(31 downto 0) := (others => '0');
+signal opa_i, opb_i : std_logic_vector(FP_WIDTH-1 downto 0) := (others => '0');
signal fpu_op_i : std_logic_vector(2 downto 0) := (others => '0');
signal rmode_i : std_logic_vector(1 downto 0) := (others => '0');
-signal output_o : std_logic_vector(31 downto 0) := (others => '0');
-signal start_i, ready_o : std_logic := '0';
-signal ine_o, overflow_o, underflow_o, div_zero_o, inf_o, zero_o, qnan_o, snan_o: std_logic := '0';
+signal output_o : std_logic_vector(FP_WIDTH-1 downto 0) := (others => '0');
+signal start_i : std_logic := '1';
+signal ready_o : std_logic := '1';
+signal ine_o : std_logic := '0';
+signal overflow_o : std_logic := '0';
+signal underflow_o : std_logic := '0';
+signal div_zero_o : std_logic := '0';
+signal inf_o : std_logic := '0';
+signal zero_o : std_logic := '0';
+signal qnan_o : std_logic := '0';
+signal snan_o : std_logic := '0';
-signal slv_out : std_logic_vector(31 downto 0);
+signal slv_out : std_logic_vector(FP_WIDTH-1 downto 0);
constant CLK_PERIOD :time := 10 ns; -- period of clk period
file input_file: TEXT open read_mode is "STD_INPUT";
variable file_line: line;
- variable str_in: string(8 downto 1);
+ variable str_in: string(FP_WIDTH/4 downto 1);
variable str_fpu_op: string(3 downto 1);
variable str_rmode: string(2 downto 1);
begin
-- Read ops from input_file
+ --print(str(ZERO_VECTOR));
+ --print(str(INF));
+ --print(str(QNAN));
+ --print(str(SNAN));
start_i <= '0';
while not endfile(input_file) loop
-------------------------------------------------------------------------------
---
--- Project: <Floating Point Unit Core>
---
-- Description: pre-normalization entity for the square-root unit
--------------------------------------------------------------------------------
---
--- 100101011010011100100
--- 110000111011100100000
--- 100000111011000101101
--- 100010111100101111001
--- 110000111011101101001
--- 010000001011101001010
--- 110100111001001100001
--- 110111010000001100111
--- 110110111110001011101
--- 101110110010111101000
--- 100000010111000000000
---
--- Author: Jidan Al-eryani
---
--- Copyright (C) 2006
---
--- This source file may be used and distributed without
--- restriction provided that this copyright statement is not
--- removed from the file and that any derivative work contains
--- the original copyright notice and the associated disclaimer.
---
--- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
--- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
--- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
--- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
--- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
--- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
--- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
--- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
--- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
--- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
--- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
+-- See COPYRIGHT.jop
library ieee ;
use ieee.std_logic_1164.all;
begin
- s_expa <= opa_i(30 downto 23);
- s_fracta <= opa_i(22 downto 0);
+ s_expa <= opa_i(FP_WIDTH-2 downto FRAC_WIDTH);
+ s_fracta <= opa_i(FRAC_WIDTH-1 downto 0);
- exp_o <= s_exp_o(7 downto 0);
+ exp_o <= s_exp_o(EXP_WIDTH-1 downto 0);
fracta_52_o <= s_fracta_52_o;
-- opa or opb is denormalized
begin
if rising_edge(clk_i) then
if or_reduce(opa_i(30 downto 0))='1' then
- s_exp_o <= ("0"&s_exp_tem(8 downto 1));
+ s_exp_o <= ("0"&s_exp_tem(EXP_WIDTH downto 1));
else
s_exp_o <= "000000000";
end if;
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