1 -------------------------------------------------------------------------------
2 -- Description: component package
6 use ieee.std_logic_1164.all;
7 use ieee.std_logic_unsigned.all;
14 --- NOTE: I have kept the original naming convention (ie: The names include the number of bits if we were using single precision IEEE floats)
16 --- Constants --- -- carry(1) & hidden(1) & fraction(FRAC_WIDTH) & guard(1) & round(1) & sticky(1)
17 constant FRAC_COMP_WIDTH : integer := 1 + 1 + FRAC_WIDTH + 1 + 1 + 1;
19 --- Component Declartions ---
21 --***Add/Substract units***
23 component pre_norm_addsub is
24 port(clk_i : in std_logic;
25 opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
26 opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
28 fracta_28_o : out std_logic_vector(FRAC_COMP_WIDTH-1 downto 0);
29 fractb_28_o : out std_logic_vector(FRAC_COMP_WIDTH-1 downto 0);
30 exp_o : out std_logic_vector(EXP_WIDTH-1 downto 0));
33 component addsub_28 is
34 port(clk_i : in std_logic;
35 fpu_op_i : in std_logic;
36 fracta_i : in std_logic_vector(FRAC_COMP_WIDTH-1 downto 0); -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
37 fractb_i : in std_logic_vector(FRAC_COMP_WIDTH-1 downto 0);
38 signa_i : in std_logic;
39 signb_i : in std_logic;
40 fract_o : out std_logic_vector(FRAC_COMP_WIDTH-1 downto 0);
41 sign_o : out std_logic);
44 component post_norm_addsub is
45 port(clk_i : in std_logic;
46 opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
47 opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
48 fract_28_i : in std_logic_vector(FRAC_COMP_WIDTH-1 downto 0); -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
49 exp_i : in std_logic_vector(EXP_WIDTH-1 downto 0);
50 sign_i : in std_logic;
51 fpu_op_i : in std_logic;
52 rmode_i : in std_logic_vector(1 downto 0);
53 output_o : out std_logic_vector(FP_WIDTH-1 downto 0);
58 --***Multiplication units***
60 component pre_norm_mul is
63 opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
64 opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
65 exp_10_o : out std_logic_vector(9 downto 0);
66 fracta_24_o : out std_logic_vector(FRAC_WIDTH downto 0); -- hidden(1) & fraction(23)
67 fractb_24_o : out std_logic_vector(FRAC_WIDTH downto 0)
74 fracta_i : in std_logic_vector(FRAC_WIDTH downto 0); -- hidden(1) & fraction(23)
75 fractb_i : in std_logic_vector(FRAC_WIDTH downto 0);
76 signa_i : in std_logic;
77 signb_i : in std_logic;
78 start_i : in std_logic;
79 fract_o : out std_logic_vector(2*FRAC_WIDTH+1 downto 0);
80 sign_o : out std_logic;
81 ready_o : out std_logic
85 component serial_mul is
88 fracta_i : in std_logic_vector(FRAC_WIDTH downto 0); -- hidden(1) & fraction(23)
89 fractb_i : in std_logic_vector(FRAC_WIDTH downto 0);
90 signa_i : in std_logic;
91 signb_i : in std_logic;
92 start_i : in std_logic;
93 fract_o : out std_logic_vector(2*FRAC_WIDTH+1 downto 0);
94 sign_o : out std_logic;
95 ready_o : out std_logic
99 component post_norm_mul is
101 clk_i : in std_logic;
102 opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
103 opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
104 exp_10_i : in std_logic_vector(9 downto 0);
105 fract_48_i : in std_logic_vector(2*FRAC_WIDTH+1 downto 0); -- hidden(1) & fraction(23)
106 sign_i : in std_logic;
107 rmode_i : in std_logic_vector(1 downto 0);
108 output_o : out std_logic_vector(FP_WIDTH-1 downto 0);
109 ine_o : out std_logic
113 --***Division units***
115 component pre_norm_div is
117 clk_i : in std_logic;
118 opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
119 opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
120 exp_10_o : out std_logic_vector(EXP_WIDTH+1 downto 0);
121 dvdnd_50_o : out std_logic_vector(2*(FRAC_WIDTH+2)-1 downto 0);
122 dvsor_27_o : out std_logic_vector(FRAC_WIDTH+3 downto 0)
126 component serial_div is
128 clk_i : in std_logic;
129 dvdnd_i : in std_logic_vector(2*(FRAC_WIDTH+2)-1 downto 0); -- hidden(1) & fraction(23)
130 dvsor_i : in std_logic_vector(FRAC_WIDTH+3 downto 0);
131 sign_dvd_i : in std_logic;
132 sign_div_i : in std_logic;
133 start_i : in std_logic;
134 ready_o : out std_logic;
135 qutnt_o : out std_logic_vector(FRAC_WIDTH+3 downto 0);
136 rmndr_o : out std_logic_vector(FRAC_WIDTH+3 downto 0);
137 sign_o : out std_logic;
138 div_zero_o : out std_logic
142 component post_norm_div is
144 clk_i : in std_logic;
145 opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
146 opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
147 qutnt_i : in std_logic_vector(FRAC_WIDTH+3 downto 0);
148 rmndr_i : in std_logic_vector(FRAC_WIDTH+3 downto 0);
149 exp_10_i : in std_logic_vector(EXP_WIDTH+1 downto 0);
150 sign_i : in std_logic;
151 rmode_i : in std_logic_vector(1 downto 0);
152 output_o : out std_logic_vector(FP_WIDTH-1 downto 0);
153 ine_o : out std_logic
160 component pre_norm_sqrt is
162 clk_i : in std_logic;
163 opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
164 fracta_52_o : out std_logic_vector(2*(FRAC_COMP_WIDTH-2)-1 downto 0);
165 exp_o : out std_logic_vector(EXP_WIDTH-1 downto 0));
169 generic (RD_WIDTH: integer; SQ_WIDTH: integer); -- SQ_WIDTH = RD_WIDTH/2 (+ 1 if odd)
171 clk_i : in std_logic;
172 rad_i : in std_logic_vector(RD_WIDTH-1 downto 0); -- hidden(1) & fraction(23)
173 start_i : in std_logic;
174 ready_o : out std_logic;
175 sqr_o : out std_logic_vector(SQ_WIDTH-1 downto 0);
176 ine_o : out std_logic);
180 component post_norm_sqrt is
181 port( clk_i : in std_logic;
182 opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
183 fract_26_i : in std_logic_vector(FRAC_WIDTH+2 downto 0); -- hidden(1) & fraction(11)
184 exp_i : in std_logic_vector(EXP_WIDTH-1 downto 0);
185 ine_i : in std_logic;
186 rmode_i : in std_logic_vector(1 downto 0);
187 output_o : out std_logic_vector(FP_WIDTH-1 downto 0);
188 ine_o : out std_logic);