1 -------------------------------------------------------------------------------
3 -- Project: <Floating Point Unit Core>
5 -- Description: division entity for the division unit
6 -------------------------------------------------------------------------------
8 -- 100101011010011100100
9 -- 110000111011100100000
10 -- 100000111011000101101
11 -- 100010111100101111001
12 -- 110000111011101101001
13 -- 010000001011101001010
14 -- 110100111001001100001
15 -- 110111010000001100111
16 -- 110110111110001011101
17 -- 101110110010111101000
18 -- 100000010111000000000
20 -- Author: Jidan Al-eryani
25 -- This source file may be used and distributed without
26 -- restriction provided that this copyright statement is not
27 -- removed from the file and that any derivative work contains
28 -- the original copyright notice and the associated disclaimer.
30 -- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
31 -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
32 -- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
33 -- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
34 -- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
35 -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36 -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
37 -- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
38 -- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
39 -- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
41 -- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
42 -- POSSIBILITY OF SUCH DAMAGE.
46 use ieee.std_logic_1164.all;
47 use ieee.std_logic_unsigned.all;
48 use ieee.std_logic_misc.all;
57 dvdnd_i : in std_logic_vector(2*(FRAC_WIDTH+2)-1 downto 0); -- hidden(1) & fraction(23)
58 dvsor_i : in std_logic_vector(FRAC_WIDTH+3 downto 0);
59 sign_dvd_i : in std_logic;
60 sign_div_i : in std_logic;
61 start_i : in std_logic;
62 ready_o : out std_logic;
63 qutnt_o : out std_logic_vector(FRAC_WIDTH+3 downto 0);
64 rmndr_o : out std_logic_vector(FRAC_WIDTH+3 downto 0);
65 sign_o : out std_logic;
66 div_zero_o : out std_logic
70 architecture rtl of serial_div is
72 type t_state is (waiting,busy);
74 signal s_qutnt_o, s_rmndr_o : std_logic_vector(FRAC_WIDTH+3 downto 0);
76 signal s_dvdnd_i : std_logic_vector(2*(FRAC_WIDTH+2)-1 downto 0);
77 signal s_dvsor_i : std_logic_vector(FRAC_WIDTH+3 downto 0);
78 signal s_sign_dvd_i, s_sign_div_i, s_sign_o : std_logic;
79 signal s_div_zero_o : std_logic;
80 signal s_start_i, s_ready_o : std_logic;
81 signal s_state : t_state;
82 signal s_count : integer range 0 to FRAC_WIDTH+3;
83 signal s_dvd : std_logic_vector(FRAC_WIDTH+3 downto 0);
91 if rising_edge(clk_i) then
94 s_sign_dvd_i<= sign_dvd_i;
95 s_sign_div_i<= sign_div_i;
103 -- if rising_edge(clk_i) then
104 qutnt_o <= s_qutnt_o;
105 rmndr_o <= s_rmndr_o;
107 ready_o <= s_ready_o;
108 div_zero_o <= s_div_zero_o;
112 s_sign_o <= sign_dvd_i xor sign_div_i;
113 s_div_zero_o <= '1' when or_reduce(s_dvsor_i)='0' and or_reduce(s_dvdnd_i)='1' else '0';
118 if rising_edge(clk_i) then
119 if s_start_i ='1' then
122 elsif s_count=0 and s_state=busy then
126 elsif s_state=busy then
127 s_count <= s_count - 1;
137 variable v_div : std_logic_vector(26 downto 0);
139 if rising_edge(clk_i) then
141 if s_start_i ='1' then
142 s_qutnt_o <= (others =>'0');
143 s_rmndr_o <= (others =>'0');
144 elsif s_state=busy then
146 v_div := "000" & s_dvdnd_i(49 downto 26);
150 if v_div < s_dvsor_i then
151 s_qutnt_o(s_count) <= '0';
153 s_qutnt_o(s_count) <= '1';
154 v_div:=v_div-s_dvsor_i;
157 s_dvd <= v_div(25 downto 0)&'0';