# File opened at 2012-09-12 11:32:08.423984
# aquire[DAC_Settle] = 0.0
# aquire[open_files] = [<open file '2012-09-12/113208.dat', mode 'w' at 0x1d31c00>]
# aquire[DAC_Sweep] = 4000
# aquire[ADC_Averages] = 200
# aquire[start_date] = 2012-09-12
# Parameters:
# Chamber Pressure = 8.03e-08
# Venault Voltage = 18.49
# Title = Filament warm up
# Comment = Heating current increased to 1.15A over 1min
# Accelerating Voltage = 132.2
# Focus Voltage = -3.02
# Deflection Voltage = 4.24
# Initial Voltage = max
# Heating Current = 1.15
# Heating Voltage (across filament) = Not known yet
# Heating Voltage (across power supply) = Unknown
# 602 Zero = 0.00
# 602 Scale = 1e-6 x 0.1
# 602 0.1 Battery = 7.78
# 602 0.03 Battery = 7.78
# 602 0.01 Battery = 7.88
# 602 0.003 Battery = 7.88
# 602 0.001 Battery = 8.20
# ADC Regulator = 3.32
# Sample = Au on Si (125min 3.5A 3-6e-8mbar)
# Sample Angle = 135
# Data = time DAC ADC5 ADC5_sigma
# Parameters last checked = 2012-09-12 11:32:08.418109

# Experiment 2012-09-12 11:32:08.955572
# Polling for Nones.

# Data:
# time	DAC	ADC5
2.57111358643	4000	0.0	0.0
2.77167797089	4000	0.0	0.0
2.97172451019	4000	0.0	0.0
3.17412495613	4000	0.0	0.0
3.37771606445	4000	0.0	0.0
3.57926464081	4000	0.0	0.0
3.77928304672	4000	0.0	0.0
3.98179388046	4000	0.0	0.0
4.18575406075	4000	0.0	0.0
4.38980960846	4000	0.0	0.0
4.59505295753	4000	0.0	0.0
4.79586839676	4000	0.0	0.0
4.99773406982	4000	0.0	0.0
5.19923400879	4000	0.0	0.0
5.399477005	4000	0.0	0.0
5.59998512268	4000	0.0	0.0
5.80201554298	4000	0.0	0.0
6.00542736053	4000	0.0	0.0
6.20946002007	4000	0.0	0.0
6.41149616241	4000	0.0	0.0
6.65473651886	4000	0.0	0.0
6.85801196098	4000	0.0	0.0
7.06202793121	4000	0.0	0.0
7.26556062698	4000	0.0	0.0
7.46758985519	4000	0.0	0.0
7.66961193085	4000	0.0	0.0
7.87410163879	4000	0.0	0.0
8.11546945572	4000	0.0	0.0
8.31768035889	4000	0.0	0.0
8.52229070663	4000	0.0	0.0
8.72621917725	4000	0.0	0.0
8.93021726608	4000	0.0	0.0
9.13406133652	4000	0.0	0.0
9.34265232086	4000	0.0	0.0
9.54630255699	4000	0.0	0.0
9.75031495094	4000	0.0	0.0
9.95388555527	4000	0.0	0.0
10.1558613777	4000	0.0	0.0
10.3578875065	4000	0.0	0.0
10.5619001389	4000	0.0	0.0
10.7658984661	4000	0.0	0.0
10.9684770107	4000	0.0	0.0
11.1705219746	4000	0.0	0.0
11.3739855289	4000	0.0	0.0
11.5779995918	4000	0.0	0.0
# Recieved KILL signal.
# Reason: Change plot from ADC vs DAC to ADC vs Time
# File closed at 2012-09-12 11:32:31.326227