X-Git-Url: https://git.ucc.asn.au/?a=blobdiff_plain;f=Kernel%2Farch%2Fx86_64%2Flib.c;h=5b9609a6dfbf03d8cb8bd09f983c4ab000cb9f72;hb=13cfd41138fbb925b9a9e239ecd58d1a768ac5aa;hp=75d544b6b64b9fd1fa66ac36f87caaafb4f6e49b;hpb=9c61cf12758c0977ee1dc5791cba638fd3437ba6;p=tpg%2Facess2.git diff --git a/Kernel/arch/x86_64/lib.c b/Kernel/arch/x86_64/lib.c index 75d544b6..5b9609a6 100644 --- a/Kernel/arch/x86_64/lib.c +++ b/Kernel/arch/x86_64/lib.c @@ -240,6 +240,7 @@ Uint32 ind(Uint16 Port) } // === Endianness === +/* Uint32 BigEndian32(Uint32 Value) { Uint32 ret; @@ -254,6 +255,7 @@ Uint16 BigEndian16(Uint16 Value) { return (Value>>8)|(Value<<8); } +*/ // === Memory Manipulation === int memcmp(const void *__dest, const void *__src, size_t __count) @@ -317,22 +319,22 @@ int memcmp(const void *__dest, const void *__src, size_t __count) void *memcpy(void *__dest, const void *__src, size_t __count) { - if( ((tVAddr)__dest & 7) != ((tVAddr)__src & 7) ) - __asm__ __volatile__ ("rep movsb" : : "D"(__dest),"S"(__src),"c"(__count)); - else { - const Uint8 *src = __src; - Uint8 *dst = __dest; - while( (tVAddr)src & 7 && __count ) { - *dst++ = *src++; + tVAddr dst = (tVAddr)__dest, src = (tVAddr)__src; + if( (dst & 7) != (src & 7) ) + { + __asm__ __volatile__ ("rep movsb" : : "D"(dst),"S"(src),"c"(__count)); + } + else + { + while( (src & 7) && __count ) { + *(char*)dst++ = *(char*)src++; __count --; } - __asm__ __volatile__ ("rep movsq" : : "D"(dst),"S"(src),"c"(__count/8)); - src += __count & ~7; - dst += __count & ~7; + __asm__ __volatile__ ("rep movsq" : "=D"(dst),"=S"(src) : "0"(dst),"1"(src),"c"(__count/8)); __count = __count & 7; while( __count-- ) - *dst++ = *src++; + *(char*)dst++ = *(char*)src++; } return __dest; } @@ -359,3 +361,15 @@ void *memsetd(void *__dest, Uint32 __val, size_t __count) return __dest; } +Uint64 DivMod64U(Uint64 Num, Uint64 Den, Uint64 *Rem) +{ + Uint64 ret, rem; + __asm__ __volatile__( + "div %4" + : "=a" (ret), "=d" (rem) + : "a" ( Num ), "d" (0), "r" (Den) + ); + if(Rem) *Rem = rem; + return ret; +} +