X-Git-Url: https://git.ucc.asn.au/?a=blobdiff_plain;f=KernelLand%2FModules%2FDisplay%2FTegra2Vid%2Fmain.c;h=e19a5ff7eb7c6fb915c29377c72a850714140243;hb=fd61b8c2f5e94da0265b3885525beff8e86317f6;hp=41afc7f42ffd9b090d03087d2c367c51417afc29;hpb=70a143a9de252ddc4f148866b0a93e28904073e5;p=tpg%2Facess2.git diff --git a/KernelLand/Modules/Display/Tegra2Vid/main.c b/KernelLand/Modules/Display/Tegra2Vid/main.c index 41afc7f4..e19a5ff7 100644 --- a/KernelLand/Modules/Display/Tegra2Vid/main.c +++ b/KernelLand/Modules/Display/Tegra2Vid/main.c @@ -3,6 +3,7 @@ * - Driver core */ #define DEBUG 0 +#define DUMP_REGISTERS 1 #define VERSION ((0<<8)|10) #include #include @@ -63,6 +64,11 @@ tDrvUtil_Video_BufInfo gTegra2Vid_DrvUtil_BufInfo; tVideo_IOCtl_Pos gTegra2Vid_CursorPos; // === CODE === +inline void _dumpreg(int i) +{ + Log_Debug("Tegra2Vid", "[0x%03x] = 0x%08x (%s)", i, gpTegra2Vid_IOMem[i], + (csaTegra2Vid_RegisterNames[i] ? csaTegra2Vid_RegisterNames[i] : "-")); +} /** */ int Tegra2Vid_Install(char **Arguments) @@ -71,33 +77,23 @@ int Tegra2Vid_Install(char **Arguments) // KeyVal_Parse(&gTegra2Vid_KeyValueParser, Arguments); gpTegra2Vid_IOMem = (void*)MM_MapHWPages(gTegra2Vid_PhysBase, 256/4); - #if 0 + #if DUMP_REGISTERS { Log_Debug("Tegra2Vid", "Display CMD Registers"); - for( int i = 0x000; i <= 0x01A; i ++ ) - Log_Debug("Tegra2Vid", "[0x%03x] = 0x%08x", i, gpTegra2Vid_IOMem[i]); - for( int i = 0x028; i <= 0x043; i ++ ) - Log_Debug("Tegra2Vid", "[0x%03x] = 0x%08x", i, gpTegra2Vid_IOMem[i]); + for( int i = 0x000; i <= 0x01A; i ++ ) _dumpreg(i); + for( int i = 0x028; i <= 0x043; i ++ ) _dumpreg(i); Log_Debug("Tegra2Vid", "Display COM Registers"); - for( int i = 0x300; i <= 0x329; i ++ ) - Log_Debug("Tegra2Vid", "[0x%03x] = 0x%08x", i, gpTegra2Vid_IOMem[i]); + for( int i = 0x300; i <= 0x329; i ++ ) _dumpreg(i); Log_Debug("Tegra2Vid", "Display DISP Registers"); - for( int i = 0x400; i <= 0x446; i ++ ) - Log_Debug("Tegra2Vid", "[0x%03x] = 0x%08x", i, gpTegra2Vid_IOMem[i]); - for( int i = 0x480; i <= 0x484; i ++ ) - Log_Debug("Tegra2Vid", "[0x%03x] = 0x%08x", i, gpTegra2Vid_IOMem[i]); - for( int i = 0x4C0; i <= 0x4C1; i ++ ) - Log_Debug("Tegra2Vid", "[0x%03x] = 0x%08x", i, gpTegra2Vid_IOMem[i]); - + for( int i = 0x400; i <= 0x446; i ++ ) _dumpreg(i); + for( int i = 0x480; i <= 0x484; i ++ ) _dumpreg(i); + for( int i = 0x4C0; i <= 0x4C1; i ++ ) _dumpreg(i); Log_Debug("Tegra2Vid", "WINC_A Registers"); - for( int i = 0x700; i <= 0x714; i ++ ) - Log_Debug("Tegra2Vid", "[0x%03x] = 0x%08x", i, gpTegra2Vid_IOMem[i]); + for( int i = 0x700; i <= 0x714; i ++ ) _dumpreg(i); Log_Debug("Tegra2Vid", "WINBUF_A"); - for( int i = 0x800; i <= 0x80A; i ++ ) - Log_Debug("Tegra2Vid", "[0x%03x] = 0x%08x", i, gpTegra2Vid_IOMem[i]); + for( int i = 0x800; i <= 0x80A; i ++ ) _dumpreg(i); } #endif -// return 1; // HACK!!! #if 0 @@ -120,13 +116,26 @@ int Tegra2Vid_Install(char **Arguments) ); memset(gpTegra2Vid_Framebuffer, 0xFF, 0x1000); -// gpTegra2Vid_IOMem[DC_WIN_A_WIN_OPTIONS_0] &= ~0x40; +#if 0 + gpTegra2Vid_IOMem[DC_WIN_A_WIN_OPTIONS_0] = (1 << 30); gpTegra2Vid_IOMem[DC_WIN_A_COLOR_DEPTH_0] = 12; // Could be 13 (BGR/RGB) + gpTegra2Vid_IOMem[DC_WIN_A_PRESCALED_SIZE_0] = gpTegra2Vid_IOMem[DC_WIN_A_SIZE_0]; + gpTegra2Vid_IOMem[DC_WIN_A_LINE_STRIDE_0] = + gTegra2Vid_DrvUtil_BufInfo.Pitch = + 1680*4; + gTegra2Vid_DrvUtil_BufInfo.Depth = 32; + gTegra2Vid_DrvUtil_BufInfo.Width = 1680; + gTegra2Vid_DrvUtil_BufInfo.Height = 1050; +#else + gpTegra2Vid_IOMem[DC_WIN_A_COLOR_DEPTH_0] = 13; // Could be 13 (BGR/RGB) + gpTegra2Vid_IOMem[DC_WIN_A_LINE_STRIDE_0] = + gTegra2Vid_DrvUtil_BufInfo.Pitch = 1024*4; + gTegra2Vid_DrvUtil_BufInfo.Depth = 32; gTegra2Vid_DrvUtil_BufInfo.Width = 1024; gTegra2Vid_DrvUtil_BufInfo.Height = 768; - gTegra2Vid_DrvUtil_BufInfo.Pitch = 1024*4; - gTegra2Vid_DrvUtil_BufInfo.Depth = 32; gTegra2Vid_DrvUtil_BufInfo.Framebuffer = gpTegra2Vid_Framebuffer; +#endif + gpTegra2Vid_IOMem[DC_CMD_STATE_CONTROL_0] = WIN_A_ACT_REQ; // Tegra2Vid_int_SetMode(4); @@ -309,16 +318,16 @@ int Tegra2Vid_int_SetMode(int Mode) { const struct sTegra2_Disp_Mode *mode = &caTegra2Vid_Modes[Mode]; int w = mode->W, h = mode->H; // Horizontal/Vertical Active - *(Uint32*)(gpTegra2Vid_IOMem + DC_DISP_FRONT_PORCH_0) = (mode->VFP << 16) | mode->HFP; - *(Uint32*)(gpTegra2Vid_IOMem + DC_DISP_SYNC_WIDTH_0) = (mode->HS << 16) | mode->HS; - *(Uint32*)(gpTegra2Vid_IOMem + DC_DISP_BACK_PORCH_0) = (mode->VBP << 16) | mode->HBP; - *(Uint32*)(gpTegra2Vid_IOMem + DC_DISP_DISP_ACTIVE_0) = (mode->H << 16) | mode->W; - - *(Uint32*)(gpTegra2Vid_IOMem + DC_WIN_A_POSITION_0) = 0; - *(Uint32*)(gpTegra2Vid_IOMem + DC_WIN_A_SIZE_0) = (h << 16) | w; - *(Uint32*)(gpTegra2Vid_IOMem + DC_DISP_DISP_COLOR_CONTROL_0) = 0x8; // BASE888 - *(Uint32*)(gpTegra2Vid_IOMem + DC_WIN_A_COLOR_DEPTH_0) = 12; // Could be 13 (BGR/RGB) - *(Uint32*)(gpTegra2Vid_IOMem + DC_WIN_A_PRESCALED_SIZE_0) = (h << 16) | w; + gpTegra2Vid_IOMem[DC_DISP_FRONT_PORCH_0] = (mode->VFP << 16) | mode->HFP; + gpTegra2Vid_IOMem[DC_DISP_SYNC_WIDTH_0] = (mode->HS << 16) | mode->HS; + gpTegra2Vid_IOMem[DC_DISP_BACK_PORCH_0] = (mode->VBP << 16) | mode->HBP; + gpTegra2Vid_IOMem[DC_DISP_DISP_ACTIVE_0] = (mode->H << 16) | mode->W; + + gpTegra2Vid_IOMem[DC_WIN_A_POSITION_0] = 0; + gpTegra2Vid_IOMem[DC_WIN_A_SIZE_0] = (h << 16) | w; + gpTegra2Vid_IOMem[DC_DISP_DISP_COLOR_CONTROL_0] = 0x8; // BASE888 + gpTegra2Vid_IOMem[DC_WIN_A_COLOR_DEPTH_0] = 12; // Could be 13 (BGR/RGB) + gpTegra2Vid_IOMem[DC_WIN_A_PRESCALED_SIZE_0] = (h << 16) | w; Log_Debug("Tegra2Vid", "Mode %i (%ix%i) selected", Mode, w, h); @@ -331,6 +340,7 @@ int Tegra2Vid_int_SetMode(int Mode) giTegra2Vid_FramebufferSize = w*h*4; + // TODO: Does this need RAM or unmapped space? gpTegra2Vid_Framebuffer = (void*)MM_AllocDMA( (giTegra2Vid_FramebufferSize + PAGE_SIZE-1) / PAGE_SIZE, 32, @@ -344,10 +354,12 @@ int Tegra2Vid_int_SetMode(int Mode) ); // Tell hardware - *(Uint32*)(gpTegra2Vid_IOMem + DC_WINBUF_A_START_ADDR_0) = gTegra2Vid_FramebufferPhys; - *(Uint32*)(gpTegra2Vid_IOMem + DC_WINBUF_A_ADDR_V_OFFSET_0) = 0; // Y offset - *(Uint32*)(gpTegra2Vid_IOMem + DC_WINBUF_A_ADDR_H_OFFSET_0) = 0; // X offset + gpTegra2Vid_IOMem[DC_WINBUF_A_START_ADDR_0] = gTegra2Vid_FramebufferPhys; + gpTegra2Vid_IOMem[DC_WINBUF_A_ADDR_V_OFFSET_0] = 0; // Y offset + gpTegra2Vid_IOMem[DC_WINBUF_A_ADDR_H_OFFSET_0] = 0; // X offset } + gpTegra2Vid_IOMem[DC_CMD_STATE_CONTROL_0] = WIN_A_ACT_REQ; + return 0; }