X-Git-Url: https://git.ucc.asn.au/?a=blobdiff_plain;f=KernelLand%2FModules%2FDisplay%2FTegra2Vid%2Ftegra2.h;h=9b33668ce5ac1d127a3888ccb434afdadfa9a64e;hb=36b950d17b828c7cd2e5e9dbe5fb4cbded89889c;hp=7e3fdf5c51db7791d570f38e7f0319bf513d740b;hpb=d0b4559f2936f6d9f06be0f7c3c51527a480ec0d;p=tpg%2Facess2.git

diff --git a/KernelLand/Modules/Display/Tegra2Vid/tegra2.h b/KernelLand/Modules/Display/Tegra2Vid/tegra2.h
index 7e3fdf5c..9b33668c 100644
--- a/KernelLand/Modules/Display/Tegra2Vid/tegra2.h
+++ b/KernelLand/Modules/Display/Tegra2Vid/tegra2.h
@@ -19,6 +19,7 @@ const struct sTegra2_Disp_Mode
 }	caTegra2Vid_Modes[] = {
 	// TODO: VESA timings
 	{1024, 768,  58, 4,   58,  4,   58,   4},	// 1024x768 (reset), RtS=11,4
+	{1680,1050, 104, 1,  184,  3 , 288,  33},	// 1680x1050 @ 60Hz
 	// TV Timings
 	{720,  487,  16,33,   63, 33,   59, 133},	// NTSC 2
 	{720,  576,  12,33,   63, 33,   69, 193},	// PAL 2 (VFP shown as 2/33, used 33)
@@ -160,6 +161,7 @@ enum eTegra2_Disp_Regs
 	DC_WIN_A_DDA_INCREMENT_0,
 	DC_WIN_A_LINE_STRIDE_0,
 	DC_WIN_A_BUF_STRIDE_0,
+	_DC_WIN_A_70C,
 	DC_WIN_A_BUFFER_ADDR_MODE_0,
 	DC_WIN_A_DV_CONTROL_0,
 	DC_WIN_A_BLEND_NOKEY_0,
@@ -337,6 +339,7 @@ const char * const csaTegra2Vid_RegisterNames[] = {
 	"DC_WIN_A_DDA_INCREMENT_0",
 	"DC_WIN_A_LINE_STRIDE_0",
 	"DC_WIN_A_BUF_STRIDE_0",
+	"-",
 	"DC_WIN_A_BUFFER_ADDR_MODE_0",
 	"DC_WIN_A_DV_CONTROL_0",
 	"DC_WIN_A_BLEND_NOKEY_0",