X-Git-Url: https://git.ucc.asn.au/?a=blobdiff_plain;f=KernelLand%2FModules%2FInterfaces%2FUDI%2Ftrans%2Fbus_pci.c;h=2582804f18cea4035e12a90bdb3a72fde3e011f2;hb=3bbdda25a43af7c2c97719ff7ebd9fd2187ae272;hp=daf07f27fdbc7c8f160021090a7e5a7281916303;hpb=e2ff5722101ae7dbb10f51f1477eac625fa30c1e;p=tpg%2Facess2.git

diff --git a/KernelLand/Modules/Interfaces/UDI/trans/bus_pci.c b/KernelLand/Modules/Interfaces/UDI/trans/bus_pci.c
index daf07f27..2582804f 100644
--- a/KernelLand/Modules/Interfaces/UDI/trans/bus_pci.c
+++ b/KernelLand/Modules/Interfaces/UDI/trans/bus_pci.c
@@ -5,7 +5,7 @@
  * trans/bus_pci.c
  * - PCI Bus Driver
  */
-#define DEBUG	1
+#define DEBUG	0
 #include <udi.h>
 #include <udi_physio.h>
 #include <udi_pci.h>
@@ -66,10 +66,11 @@ typedef struct
 
 	 int	interrupt_handle;
 
-	udi_pio_handle_t 	intr_preprocessing;	
+	udi_pio_handle_t 	intr_preprocessing;
 	udi_intr_event_cb_t	*event_cbs[PCI_MAX_EVENT_CBS];
-	 int	event_cb_wr_ofs;
-	 int	event_cb_rd_ofs;
+	udi_index_t	event_cb_wr_ofs;
+	udi_index_t	event_cb_rd_ofs;
+	 int	bIntrEnabled;
 } pci_child_chan_context_t;
 
 // === PROTOTYPES ===
@@ -87,6 +88,7 @@ void	pci_intr_detach_req(udi_intr_detach_cb_t *cb);
 
 void	pci_intr_ch_event_ind(udi_channel_event_cb_t *cb);
 void	pci_intr_event_rdy(udi_intr_event_cb_t *cb);
+void	pci_intr_event_rdy__irqs_enabled(udi_cb_t *gcb, udi_buf_t *newbuf, udi_status_t status, udi_ubit16_t result);
 void	pci_intr_handler(int irq, void *void_context);
 void	pci_intr_handle__trans_done(udi_cb_t *gcb, udi_buf_t *new_buf, udi_status_t status, udi_ubit16_t result);
 
@@ -154,6 +156,13 @@ void pci_enumerate_req(udi_enumerate_cb_t *cb, udi_ubit8_t enumeration_level)
 			attr_list ++;
 			DPT_SET_ATTR32(attr_list, "pci_device_id", dev);
 			attr_list ++;
+			
+			DPT_SET_ATTR32(attr_list, "pci_baseclass", class >> 16);
+			attr_list ++;
+			DPT_SET_ATTR32(attr_list, "pci_sub_class", (class >> 8) & 0xFF);
+			attr_list ++;
+			DPT_SET_ATTR32(attr_list, "pci_prog_if", (class >> 0) & 0xFF);
+			attr_list ++;
 
 			cb->attr_valid_length = attr_list - cb->attr_list;
 			cb->child_ID = rdata->cur_iter;
@@ -218,7 +227,7 @@ void pci_intr_attach_req__channel_spawned(udi_cb_t *gcb, udi_channel_t new_chann
 	
 	context->interrupt_handle = IRQ_AddHandler(
 		PCI_GetIRQ(context->child_chan_context.child_ID),
-		pci_intr_handler, new_channel);
+		pci_intr_handler, context);
 
 	udi_intr_attach_ack(cb, UDI_OK);
 }
@@ -234,6 +243,11 @@ void pci_intr_ch_event_ind(udi_channel_event_cb_t *cb)
 void pci_intr_event_rdy(udi_intr_event_cb_t *cb)
 {
 	pci_child_chan_context_t	*context = UDI_GCB(cb)->context;
+
+	ASSERTC(context->event_cb_rd_ofs, <, PCI_MAX_EVENT_CBS);
+	ASSERTC(context->event_cb_wr_ofs, <, PCI_MAX_EVENT_CBS);
+
+	LOG("Rd %i, Wr %i [WR %p]", context->event_cb_rd_ofs, context->event_cb_wr_ofs, cb);
 	if( context->event_cbs[context->event_cb_wr_ofs] )
 	{
 		// oops, overrun.
@@ -242,22 +256,40 @@ void pci_intr_event_rdy(udi_intr_event_cb_t *cb)
 	context->event_cbs[context->event_cb_wr_ofs++] = cb;
 	if( context->event_cb_wr_ofs == PCI_MAX_EVENT_CBS )
 		context->event_cb_wr_ofs = 0;
+	
+	// TODO: Fire once >= min_event_pend CBs are recieved
+	if( !context->bIntrEnabled )
+	{
+		context->bIntrEnabled = 1;
+		udi_pio_trans(pci_intr_event_rdy__irqs_enabled, NULL, context->intr_preprocessing, 0, NULL, NULL);
+	}
+}
+void pci_intr_event_rdy__irqs_enabled(udi_cb_t *gcb, udi_buf_t *newbuf, udi_status_t status, udi_ubit16_t result)
+{
+	// nothing
 }
 
 void pci_intr_handler(int irq, void *void_context)
 {
 	pci_child_chan_context_t *context = void_context;
 
+	LOG("irq=%i, context=%p", irq, context);
+
 	if( context->event_cb_rd_ofs == context->event_cb_wr_ofs ) {
 		// Dropped
 		return ;
 	}
 
+	ASSERTC(context->event_cb_rd_ofs, <, PCI_MAX_EVENT_CBS);
+	ASSERTC(context->event_cb_wr_ofs, <, PCI_MAX_EVENT_CBS);
+
 	udi_intr_event_cb_t *cb = context->event_cbs[context->event_cb_rd_ofs];
+	LOG("Rd %i, Wr %i [RD %p]", context->event_cb_rd_ofs, context->event_cb_wr_ofs, cb);
 	context->event_cbs[context->event_cb_rd_ofs] = NULL;
 	context->event_cb_rd_ofs ++;
 	if( context->event_cb_rd_ofs == PCI_MAX_EVENT_CBS )
 		context->event_cb_rd_ofs = 0;
+	ASSERT(cb);
 	
 	if( UDI_HANDLE_IS_NULL(context->intr_preprocessing, udi_pio_handle_t) )
 	{
@@ -296,14 +328,20 @@ udi_status_t pci_pio_do_io(uint32_t child_ID, udi_ubit32_t regset_idx, udi_ubit3
 		// TODO:
 		return UDI_STAT_NOT_SUPPORTED;
 	case UDI_PCI_BAR_0 ... UDI_PCI_BAR_5: {
-		Uint64 bar = PCI_GetBAR(pciid, regset_idx);
+		Uint32 bar = PCI_GetBAR(pciid, regset_idx);
 		if(bar & 1)
 		{
 			// IO BAR
 			bar &= ~3;
 			#define _IO(fc, type) do {\
-				if( isOutput )	out##fc(bar+ofs, *(type*)data); \
-				else	*(type*)data = in##fc(bar+ofs); \
+				if( isOutput ) { \
+					/*LOG("out"#fc"(0x%x, 0x%x)",bar+ofs,*(type*)data);*/\
+					out##fc(bar+ofs, *(type*)data); \
+				} \
+				else { \
+					*(type*)data = in##fc(bar+ofs); \
+					/*LOG("in"#fc"(0x%x) = 0x%x",bar+ofs,*(type*)data);*/\
+				}\
 				} while(0)
 			switch(len)
 			{
@@ -319,7 +357,7 @@ udi_status_t pci_pio_do_io(uint32_t child_ID, udi_ubit32_t regset_idx, udi_ubit3
 		else
 		{
 			// Memory BAR
-			bar = PCI_GetValidBAR(pciid, regset_idx, PCI_BARTYPE_MEM);
+			//Uint64 longbar = PCI_GetValidBAR(pciid, regset_idx, PCI_BARTYPE_MEM);
 			return UDI_STAT_NOT_SUPPORTED;
 		}
 		break; }
@@ -353,7 +391,7 @@ udi_primary_init_t	pci_pri_init = {
 	.mgmt_ops = &pci_mgmt_ops,
 	.mgmt_op_flags = pci_mgmt_op_flags,
 	.mgmt_scratch_requirement = 0,
-	.enumeration_attr_list_length = 4,
+	.enumeration_attr_list_length = 7,
 	.rdata_size = sizeof(pci_rdata_t),
 	.child_data_size = 0,
 	.per_parent_paths = 0