X-Git-Url: https://git.ucc.asn.au/?a=blobdiff_plain;f=KernelLand%2FModules%2FNetwork%2FVIARhineII%2Frhine2_hw.h;h=f6a92f47e8fff33ab64039066dc0074e50b18ff5;hb=be5123fe1f4aa66b76ce8ef589362ad21b6bbf72;hp=afe9cc9e7040e2780e28e21800cef11bfca69ed5;hpb=385aa5c4b5e509d298b3341dcd27ca26c3ce2358;p=tpg%2Facess2.git

diff --git a/KernelLand/Modules/Network/VIARhineII/rhine2_hw.h b/KernelLand/Modules/Network/VIARhineII/rhine2_hw.h
index afe9cc9e..f6a92f47 100644
--- a/KernelLand/Modules/Network/VIARhineII/rhine2_hw.h
+++ b/KernelLand/Modules/Network/VIARhineII/rhine2_hw.h
@@ -45,6 +45,42 @@ enum eRegs
 #define TCR_RSVD1	(1 << 4)	// reserved
 #define TCR_TRSF(v)	(((v)&7)<<5)	// Transmit FIFO threshold
 
+#define CR0_INIT	(1 << 0)
+#define CR0_STRT	(1 << 1)
+#define CR0_STOP	(1 << 2)
+#define CR0_RXON	(1 << 3)
+#define CR0_TXON	(1 << 4)
+#define CR0_TDMD	(1 << 5)
+#define CR0_RDMD	(1 << 6)
+#define CR0_RESV	(1 << 7)	// reserved
+
+#define CR1_EREN	(1 << 0)	// Early recieve enable
+#define CR1_RESV0	(1 << 1)
+#define CR1_FDX 	(1 << 2)	// Full/Half-duplex selector
+#define CR1_DPOLL	(1 << 3)	// Disable automatic polling
+#define CR1_RESV1	(1 << 4)
+#define CR1_TDMD	(1 << 5)
+#define CR1_RDMD	(1 << 6)
+#define CR1_SFRST	(1 << 7)	// Software reset
+
+#define ISR0_PRX	(1 << 0)	// Packet recieved
+#define ISR0_PTX	(1 << 1)	// Packet transmitted successfully
+#define ISR0_RXE	(1 << 2)	// RX Error
+#define ISR0_TXE	(1 << 3)	// TX Error
+#define ISR0_TU 	(1 << 4)	// Transmit buffer underflow
+#define ISR0_RU 	(1 << 5)	// Recieve buffer link error
+#define ISR0_BE 	(1 << 6)	// PCI Bus error
+#define ISR0_CNT	(1 << 7)	// CRC error / missed packet counter overflow
+
+#define ISR1_ERI	(1 << 0)	// Early recieve interrupt
+#define ISR1_UDFI	(1 << 1)	// TX FIFO underflow event
+#define ISR1_OVFI	(1 << 2)	// Recieve overflow
+#define ISR1_PKTR	(1 << 3)	// FIFO overflow (?"next packet race with current packet")
+#define ISR1_NORBF	(1 << 4)	// No more recieve buffers avaiable (overflow essentialy)
+#define ISR1_ABTI	(1 << 5)	// Transmission abort due to excessive collisions
+#define ISR1_SRCI	(1 << 6)	// Port state change
+#define ISR1_GENI	(1 << 7)	// General purpose interrupt
+
 // TODO: Other Regs?
 
 struct sRXDesc
@@ -55,7 +91,7 @@ struct sRXDesc
 	Uint16	_resvd;
 	Uint32	RXBufferStart;
 	Uint32	RDBranchAddress;	// ? - I'm guessing it's the next descriptor in the chain
-};
+} PACKED;
 
 #define RSR_RERR	(1 << 0)	// Receiver error
 #define RSR_CRC 	(1 << 1)	// CRC Error
@@ -82,12 +118,14 @@ struct sTXDesc
 	Uint8	_resvd;
 	Uint32	TXBufferStart;
 	Uint32	TDBranchAddress;	// Bit 0: Disable interrupt
-};
+} PACKED;
 
 #define TD_TCR_CRC	(1 << 0)	// Disable CRC generation
 #define TD_TCR_STP	(1 << 5)	// First descriptor in packet
 #define TD_TCR_EDP	(1 << 6)	// Last descriptor in packet
 #define TD_TCR_IC	(1 << 7)	// Interrupt when transmitted
 
+#define TD_TSR_OWN	(1 << 31)
+
 #endif