X-Git-Url: https://git.ucc.asn.au/?a=blobdiff_plain;f=KernelLand%2FModules%2FStorage%2FAHCI%2Fahci.h;h=81b6059e3dc17a799d69f79a77df7483e7fe250e;hb=c00f6ece0ff9a1ad2d07691122070d52d4397d78;hp=cfed404ce73416cba77455b1592d2ceb6f6cad2c;hpb=d8257630a3e339fbd878fefaaad3e650be2aad88;p=tpg%2Facess2.git

diff --git a/KernelLand/Modules/Storage/AHCI/ahci.h b/KernelLand/Modules/Storage/AHCI/ahci.h
index cfed404c..81b6059e 100644
--- a/KernelLand/Modules/Storage/AHCI/ahci.h
+++ b/KernelLand/Modules/Storage/AHCI/ahci.h
@@ -8,47 +8,54 @@
 #ifndef _AHCI__AHCI_H_
 #define _AHCI__AHCI_H_
 
-#define AHCI_CAP_S64A	(1 << 31)	// Supports 64-bit addressing
-#define AHCI_CAP_SNCQ	(1 << 30)	// Supports Native Command Queuing
-#define AHCI_CAP_SXS	(1 << 5)	// Support External SATA
+#include "ahci_hw.h"
+#include <Storage/LVM/include/lvm.h>
+#include <stdbool.h>
+#include <mutex.h>
+#include <semaphore.h>
+#include <events.h>
 
-struct sAHCI_MemSpace
+typedef struct sAHCI_Ctrlr	tAHCI_Ctrlr;
+typedef struct sAHCI_Port	tAHCI_Port;
+
+struct sAHCI_Ctrlr
 {
-	Uint32	CAP;	// Host Capabilities
-	Uint32	GHC;	// Global Host Control;
-	Uint16	IS;	// Interrupt Status
-	Uint16	PI;	// Ports Implemented
-	Uint32	VS;	// Version
-	Uint32	CCC_CTL;	// Command Completion Coalsecing Control
-	Uint16	CCC_PORTS;	// Command Completion Coalsecing Ports
-	Uint32	EM_LOC;	// Enclosure Management Location
-	Uint32	CAP2;	// Host Capabilities Extended
-	Uint16	BOHC;	// BIOS/OS Handoff Control and Status
+	 int	ID;	// Controller ID
+	
+	 int	IRQ;
+	tPAddr	PMemBase;
+	tAHCI_MemSpace	*MMIO;
+	
+	bool	Supports64Bit;
+
+	 int	NCS;
 	
-	Uint16	_padding[(0x100-0x2C)/2];
-
-	struct s_port
-	{
-		Uint32	PxCLB;	// Command List Base Address
-		Uint32	PxCLBU;	// (High of above)
-		Uint32	PxFB;	// FIS Base Address
-		Uint32	PxFBU;	// (high of above)
-		Uint32	PxIS;	// Interrupt Status
-		Uint32	PxIE;	// Interrupt Enable
-		Uint32	PxCMD;	// Command and Status
-		Uint32	_resvd;
-		Uint32	PxTFD;	// Task File Data
-		Uint32	PxSIG;	// Signature
-		Uint32	PxSSTS;	// Serial ATA Status
-		Uint32	PxSCTL;	// Serial ATA Control
-		Uint32	PxSERR;	// Serial ATA Error
-		Uint32	PxSACT;	// Serial ATA Active
-		Uint32	PxCI;	// Command Issue
-		Uint32	PxSNTF;	// Serial ATA Notification
-		Uint32	PxFBS;	// FIS-based Switching Control
-		Uint32	_resvd2[(0x70-0x44)/4];
-		Uint32	PxVS[4];
-	}	Ports[32];
+	 int	PortCount;
+	tAHCI_Port	*Ports;
+};
+
+struct sAHCI_Port
+{
+	 int	Idx;	// Hardware index
+	tAHCI_Ctrlr	*Ctrlr;
+	volatile struct s_port	*MMIO;
+
+	tMutex	lCommandSlots;
+	Uint32	IssuedCommands;
+	volatile struct sAHCI_CmdHdr	*CmdList;
+	struct sAHCI_CmdTable	*CommandTables[32];
+	tThread	*CommandThreads[32];
+	volatile struct sAHCI_RcvdFIS	*RcvdFIS;
+
+	tSemaphore	InterruptSem;
+	Uint32	LastIS;
+
+	bool	bHotplug;
+	bool	bPresent;
+	bool	bATAPI;
+
+	void	*LVMHandle;
+	Uint64	SectorCount;
 };
 
 #endif