X-Git-Url: https://git.ucc.asn.au/?a=blobdiff_plain;f=KernelLand%2FModules%2FUSB%2FUHCI%2Fuhci.h;h=fbbeba32b1dca62894285e21494e183750147b54;hb=f0b5018caef356cda6afa147ddb6917068c62dd7;hp=40b589b1bed9fb83ebc11dbc08454660793e872f;hpb=0dd59ddf18248c362e351ae13c7b89bb15831ee4;p=tpg%2Facess2.git

diff --git a/KernelLand/Modules/USB/UHCI/uhci.h b/KernelLand/Modules/USB/UHCI/uhci.h
index 40b589b1..fbbeba32 100644
--- a/KernelLand/Modules/USB/UHCI/uhci.h
+++ b/KernelLand/Modules/USB/UHCI/uhci.h
@@ -8,6 +8,7 @@
 
 // === TYPES ===
 typedef struct sUHCI_Controller	tUHCI_Controller;
+typedef struct sUHCI_EndpointInfo	tUHCI_EndpointInfo;
 typedef struct sUHCI_ExtraTDInfo	tUHCI_ExtraTDInfo;
 
 typedef struct sUHCI_TD	tUHCI_TD;
@@ -24,6 +25,23 @@ struct sUHCI_ExtraTDInfo
 	void	*CallbackPtr;
 };
 
+struct sUHCI_EndpointInfo
+{
+	unsigned MaxPacketSize : 12;
+	unsigned Type : 3;
+	unsigned Tgl : 1;
+};
+
+#define TD_CTL_IOC	(1 << 24)
+#define TD_CTL_ACTIVE	(1 << 23)
+#define TD_CTL_STALLED	(1 << 22)
+#define TD_CTL_DATABUFERR	(1 << 21)
+#define TD_CTL_BABBLE	(1 << 20)
+#define TD_CTL_NAK	(1 << 19)
+#define TD_CTL_CRCERR	(1 << 18)
+#define TD_CTL_BITSTUFF	(1 << 17)
+#define TD_CTL_RESERVED	(1 << 16)
+
 struct sUHCI_TD
 {
 	/**
@@ -85,7 +103,7 @@ struct sUHCI_TD
 	{
 		tUHCI_ExtraTDInfo	*ExtraInfo;
 		char	bActive;	// Allocated
-		char	bComplete;	// Job complete
+		Uint8	QueueIndex;	// QH, 0-127 are interrupt, 128 undef, 129 Control, 130 Bulk
 		char	bFreePointer;	// Free \a BufferPointer once done
 	} _info;
 } __attribute__((aligned(16)));
@@ -102,7 +120,6 @@ struct sUHCI_QH
 	 */
 	Uint32	Next;
 
-	
 	/**
 	 * \brief Next Entry in list
 	 * 
@@ -164,9 +181,35 @@ struct sUHCI_Controller
 
 	tUSBHub	*RootHub;
 
-	tUHCI_QH	InterruptQH;
-	tUHCI_QH	ControlQH;
-	tUHCI_QH	BulkQH;
+	/**
+	 * \brief Load in bytes on each interrupt queue
+	 */
+	 int	InterruptLoad[128];
+
+	tPAddr  	PhysTDQHPage;
+	struct
+	{
+		// 127 Interrupt Queue Heads
+		// - 4ms -> 256ms range of periods
+		tUHCI_QH	InterruptQHs[0];
+		tUHCI_QH	InterruptQHs_256ms[64];
+		tUHCI_QH	InterruptQHs_128ms[32];
+		tUHCI_QH	InterruptQHs_64ms [16];
+		tUHCI_QH	InterruptQHs_32ms [ 8];
+		tUHCI_QH	InterruptQHs_16ms [ 4];
+		tUHCI_QH	InterruptQHs_8ms  [ 2];
+		tUHCI_QH	InterruptQHs_4ms  [ 1];
+		tUHCI_QH	_padding;
+	
+		tUHCI_QH	ControlQH;
+		tUHCI_QH	BulkQH;
+		
+		tUHCI_TD	LocalTDPool[ (4096-(128+2)*sizeof(tUHCI_QH)) / sizeof(tUHCI_TD) ];
+	}	*TDQHPage;
+	
+	struct {
+		tUHCI_EndpointInfo EndpointInfo[16];
+	} *DevInfo[256];
 };
 
 // === ENUMERATIONS ===