X-Git-Url: https://git.ucc.asn.au/?a=blobdiff_plain;f=Modules%2FDisplay%2FTegra2Vid%2Ftegra2.h;h=a3f126b681f5fd93e60d13c56893c37a7c514b1d;hb=a2495c6ea4f4cab16b5d339ae511428e92e89e73;hp=b5666f336f92187d83fe908a8d27e406cb0b0771;hpb=80b88a349e37b8493506c7e28cf169c9314cdbf4;p=tpg%2Facess2.git

diff --git a/Modules/Display/Tegra2Vid/tegra2.h b/Modules/Display/Tegra2Vid/tegra2.h
index b5666f33..a3f126b6 100644
--- a/Modules/Display/Tegra2Vid/tegra2.h
+++ b/Modules/Display/Tegra2Vid/tegra2.h
@@ -30,29 +30,29 @@ const int ciTegra2Vid_ModeCount = sizeof(caTegra2Vid_Modes)/sizeof(caTegra2Vid_M
 enum eTegra2_Disp_Regs
 {
 	DC_DISP_DISP_SIGNAL_OPTIONS0_0 = 0x400,
-	DC_DISP_DISP_SIGNAL_OPTIONS1_0,
-	DC_DISP_DISP_WIN_OPTIONS_0,
-	DC_DISP_MEM_HIGH_PRIORITY_0,
-	DC_DISP_MEM_HIGH_PRIORITY_TIMER_0,
-	DC_DISP_DISP_TIMING_OPTIONS_0,
-	DC_DISP_REF_TO_SYNC_0,
-	DC_DISP_SYNC_WIDTH_0,
-	DC_DISP_BACK_PORCH_0,
-	DC_DISP_DISP_ACTIVE_0,
-	DC_DISP_FRONT_PORCH_0,
+	DC_DISP_DISP_SIGNAL_OPTIONS1_0, // 401
+	DC_DISP_DISP_WIN_OPTIONS_0,	// 402
+	DC_DISP_MEM_HIGH_PRIORITY_0,	// 403
+	DC_DISP_MEM_HIGH_PRIORITY_TIMER_0,	// 404
+	DC_DISP_DISP_TIMING_OPTIONS_0,	// 405
+	DC_DISP_REF_TO_SYNC_0,  	// 406 (TrimSlice 0x0001 000B)
+	DC_DISP_SYNC_WIDTH_0,   	// 407 (TrimSlice 0x0004 003A)
+	DC_DISP_BACK_PORCH_0,   	// 408 (TrimSlice 0x0004 003A)
+	DC_DISP_DISP_ACTIVE_0,  	// 409 (TrimSlice 0x0300 0400)
+	DC_DISP_FRONT_PORCH_0,  	// 40A (TrimSlice 0x0004 003A)
 
-	DC_DISP_H_PULSE0_CONTROL_0,
+	DC_DISP_H_PULSE0_CONTROL_0,	// 40B
 
 	DC_DISP_DISP_COLOR_CONTROL_0 = 0x430,
 	
 	DC_WINC_A_COLOR_PALETTE_0 = 0x500,
 	DC_WINC_A_PALETTE_COLOR_EXT_0 = 0x600,
 	DC_WIN_A_WIN_OPTIONS_0 = 0x700,
-	DC_WIN_A_BYTE_SWAP_0,
-	DC_WIN_A_BUFFER_CONTROL_0,
-	DC_WIN_A_COLOR_DEPTH_0,
-	DC_WIN_A_POSITION_0,
-	DC_WIN_A_SIZE_0,
+	DC_WIN_A_BYTE_SWAP_0,   	// 701
+	DC_WIN_A_BUFFER_CONTROL_0,	// 702
+	DC_WIN_A_COLOR_DEPTH_0, 	// 703
+	DC_WIN_A_POSITION_0,    	// 704
+	DC_WIN_A_SIZE_0,        	// 705 (TrimSlice 0x0300 0400)
 	DC_WIN_A_PRESCALED_SIZE_0,
 	DC_WIN_A_H_INITIAL_DDA_0,
 	DC_WIN_A_V_INITIAL_DDA_0,