X-Git-Url: https://git.ucc.asn.au/?a=blobdiff_plain;f=Modules%2FDisplay%2FTegra2Vid%2Ftegra2.h;h=c36b05e7f6dea672f739e689ec69b9e2f22e073b;hb=c43646fe791455ca711ed79167c4b7fbd4346669;hp=a3f126b681f5fd93e60d13c56893c37a7c514b1d;hpb=c7fda4cfb7ada8aa0935b4e4f6c98fcb2dbb4b48;p=tpg%2Facess2.git diff --git a/Modules/Display/Tegra2Vid/tegra2.h b/Modules/Display/Tegra2Vid/tegra2.h index a3f126b6..c36b05e7 100644 --- a/Modules/Display/Tegra2Vid/tegra2.h +++ b/Modules/Display/Tegra2Vid/tegra2.h @@ -18,17 +18,51 @@ const struct sTegra2_Disp_Mode Uint16 HBP, VBP; } caTegra2Vid_Modes[] = { // TODO: VESA timings - {720, 487, 16,33, 63, 33, 59, 133}, // NTSC 2 - {720, 576, 12,33, 63, 33, 69, 193}, // PAL 2 (VFP shown as 2/33, used 33) - {720, 483, 16, 6, 63, 6, 59, 30}, // 480p - {1280, 720, 70, 5, 804, 6, 220, 20}, // 720p - {1920,1080, 44, 4, 884, 5, 148, 36}, // 1080p +// {720, 487, 16,33, 63, 33, 59, 133}, // NTSC 2 +// {720, 576, 12,33, 63, 33, 69, 193}, // PAL 2 (VFP shown as 2/33, used 33) +// {720, 483, 16, 6, 63, 6, 59, 30}, // 480p +// {1280, 720, 70, 5, 804, 6, 220, 20}, // 720p +// {1920,1080, 44, 4, 884, 5, 148, 36}, // 1080p // TODO: Can all but HA/VA be constant and those select the resolution? }; const int ciTegra2Vid_ModeCount = sizeof(caTegra2Vid_Modes)/sizeof(caTegra2Vid_Modes[0]); enum eTegra2_Disp_Regs { + DC_CMD_STATE_CONTROL_0 = 0x041, + DC_CMD_DISPLAY_WINDOW_HEADER_0, // 042 + DC_CMD_REG_ACT_CONTROL_0, // 043 + + DC_COM_CRC_CONTROL_0 = 0x300, + DC_COM_CRC_CHECKSUM_0, // 301 + DC_COM_PIN_OUTPUT_ENABLE0_0, // 302 + DC_COM_PIN_OUTPUT_ENABLE1_0, // 303 + DC_COM_PIN_OUTPUT_ENABLE2_0, // 304 + DC_COM_PIN_OUTPUT_ENABLE3_0, // 305 + DC_COM_PIN_OUTPUT_POLARITY0_0, // 306 + DC_COM_PIN_OUTPUT_POLARITY1_0, // 307 + DC_COM_PIN_OUTPUT_POLARITY2_0, // 308 + DC_COM_PIN_OUTPUT_POLARITY3_0, // 309 + DC_COM_PIN_OUTPUT_DATA0_0, // 30A + DC_COM_PIN_OUTPUT_DATA1_0, // 30B + DC_COM_PIN_OUTPUT_DATA2_0, // 30C + DC_COM_PIN_OUTPUT_DATA3_0, // 30D + DC_COM_PIN_INPUT_ENABLE0_0, // 30E + DC_COM_PIN_INPUT_ENABLE1_0, // 30F + DC_COM_PIN_INPUT_ENABLE2_0, // 310 + DC_COM_PIN_INPUT_ENABLE3_0, // 311 + DC_COM_PIN_INPUT_DATA0_0, // 312 + DC_COM_PIN_INPUT_DATA1_0, // 313 + DC_COM_PIN_OUTPUT_SELECT0_0, // 314 + DC_COM_PIN_OUTPUT_SELECT1_0, // 315 + DC_COM_PIN_OUTPUT_SELECT2_0, // 316 + DC_COM_PIN_OUTPUT_SELECT3_0, // 317 + DC_COM_PIN_OUTPUT_SELECT4_0, // 318 + DC_COM_PIN_OUTPUT_SELECT5_0, // 319 + DC_COM_PIN_OUTPUT_SELECT6_0, // 31A + DC_COM_PIN_MISC_CONTROL_0, // 31B + // TODO: Complete + DC_DISP_DISP_SIGNAL_OPTIONS0_0 = 0x400, DC_DISP_DISP_SIGNAL_OPTIONS1_0, // 401 DC_DISP_DISP_WIN_OPTIONS_0, // 402 @@ -40,11 +74,76 @@ enum eTegra2_Disp_Regs DC_DISP_BACK_PORCH_0, // 408 (TrimSlice 0x0004 003A) DC_DISP_DISP_ACTIVE_0, // 409 (TrimSlice 0x0300 0400) DC_DISP_FRONT_PORCH_0, // 40A (TrimSlice 0x0004 003A) - DC_DISP_H_PULSE0_CONTROL_0, // 40B + DC_DISP_H_PULSE0_POSITION_A_0, // 40C + DC_DISP_H_PULSE0_POSITION_B_0, // 40D + DC_DISP_H_PULSE0_POSITION_C_0, // 40E + DC_DISP_H_PULSE0_POSITION_D_0, // 40F + DC_DISP_H_PULSE1_CONTROL_0, // 410 + DC_DISP_H_PULSE1_POSITION_A_0, // 411 + DC_DISP_H_PULSE1_POSITION_B_0, // 412 + DC_DISP_H_PULSE1_POSITION_C_0, // 413 + DC_DISP_H_PULSE1_POSITION_D_0, // 414 + DC_DISP_H_PULSE2_CONTROL_0, // 415 + DC_DISP_H_PULSE2_POSITION_A_0, // 416 + DC_DISP_H_PULSE2_POSITION_B_0, // 417 + DC_DISP_H_PULSE2_POSITION_C_0, // 418 + DC_DISP_H_PULSE2_POSITION_D_0, // 419 + DC_DISP_V_PULSE0_CONTROL_0, // 41A + DC_DISP_V_PULSE0_POSITION_A_0, // 41B + DC_DISP_V_PULSE0_POSITION_B_0, // 41C + DC_DISP_V_PULSE0_POSITION_C_0, // 41D + DC_DISP_V_PULSE1_CONTROL_0, // 41E + DC_DISP_V_PULSE1_POSITION_A_0, // 41F + DC_DISP_V_PULSE1_POSITION_B_0, // 420 + DC_DISP_V_PULSE1_POSITION_C_0, // 421 + DC_DISP_V_PULSE2_CONTROL_0, // 422 + DC_DISP_V_PULSE2_POSITION_A_0, // 423 + DC_DISP_V_PULSE3_CONTROL_0, // 424 + DC_DISP_V_PULSE3_POSITION_A_0, // 425 + DC_DISP_M0_CONTROL_0, // 426 + DC_DISP_M1_CONTROL_0, // 427 + DC_DISP_DI_CONTROL_0, // 428 + DC_DISP_PP_CONTROL_0, // 429 + DC_DISP_PP_SELECT_A_0, // 42A + DC_DISP_PP_SELECT_B_0, // 42B + DC_DISP_PP_SELECT_C_0, // 42C + DC_DISP_PP_SELECT_D_0, // 42D + DC_DISP_DISP_CLOCK_CONTROL_0, // 42E + DC_DISP_DISP_INTERFACE_CONTROL_0,//42F + DC_DISP_DISP_COLOR_CONTROL_0, // 430 + DC_DISP_SHIFT_CLOCK_OPTIONS_0, // 431 + DC_DISP_DATA_ENABLE_OPTIONS_0, // 432 + DC_DISP_SERIAL_INTERFACE_OPTIONS_0, // 433 + DC_DISP_LCD_SPI_OPTIONS_0, // 434 + DC_DISP_BORDER_COLOR_0, // 435 + DC_DISP_COLOR_KEY0_LOWER_0, // 436 + DC_DISP_COLOR_KEY0_UPPER_0, // 437 + DC_DISP_COLOR_KEY1_LOWER_0, // 438 + DC_DISP_COLOR_KEY1_UPPER_0, // 439 + _DC_DISP_UNUSED_43A, + _DC_DISP_UNUSED_43B, + DC_DISP_CURSOR_FOREGROUND_0, // 43C - IMPORTANT + DC_DISP_CURSOR_BACKGROUND_0, // 43D - IMPORTANT + DC_DISP_CURSOR_START_ADDR_0, // 43E - IMPORTANT + DC_DISP_CURSOR_START_ADDR_NS_0, // 43F - IMPORTANT + DC_DISP_CURSOR_POSITION_0, // 440 - IMPORTANT + DC_DISP_CURSOR_POSITION_NS_0, // 441 - IMPORTANT + DC_DISP_INIT_SEQ_CONTROL_0, // 442 + DC_DISP_SPI_INIT_SEQ_DATA_A_0, // 443 + DC_DISP_SPI_INIT_SEQ_DATA_B_0, // 444 + DC_DISP_SPI_INIT_SEQ_DATA_C_0, // 445 + DC_DISP_SPI_INIT_SEQ_DATA_D_0, // 446 + + DC_DISP_DC_MCCIF_FIFOCTRL_0 = 0x480, + DC_DISP_MCCIF_DISPLAY0A_HYST_0, // 481 + DC_DISP_MCCIF_DISPLAY0B_HYST_0, // 482 + DC_DISP_MCCIF_DISPLAY0C_HYST_0, // 483 + DC_DISP_MCCIF_DISPLAY1B_HYST_0, // 484 + + DC_DISP_DAC_CRT_CTRL_0 = 0x4C0, + DC_DISP_DISP_MISC_CONTROL_0, // 4C1 - DC_DISP_DISP_COLOR_CONTROL_0 = 0x430, - DC_WINC_A_COLOR_PALETTE_0 = 0x500, DC_WINC_A_PALETTE_COLOR_EXT_0 = 0x600, DC_WIN_A_WIN_OPTIONS_0 = 0x700,