X-Git-Url: https://git.ucc.asn.au/?a=blobdiff_plain;f=Modules%2FStorage%2FATA%2Fio.c;h=6304cb44a6db0929679e6d8c959b459f316f37e8;hb=57c1e8ff3a5e475ff5fe457ede46a4b3598b91f2;hp=128fdca08e4b7564a640cdd04cf743a40bef7f4b;hpb=e957c67ea0f63a668303d087af7ee0c7ecff1f01;p=tpg%2Facess2.git

diff --git a/Modules/Storage/ATA/io.c b/Modules/Storage/ATA/io.c
index 128fdca0..6304cb44 100644
--- a/Modules/Storage/ATA/io.c
+++ b/Modules/Storage/ATA/io.c
@@ -285,7 +285,6 @@ int ATA_ReadDMA(Uint8 Disk, Uint64 Address, Uint Count, void *Buffer)
 	 int	disk = Disk & 1;
 	Uint16	base;
 	Sint64	timeoutTime;
-	Uint8	val;
 
 	ENTER("iDisk XAddress iCount pBuffer", Disk, Address, Count, Buffer);
 
@@ -376,9 +375,15 @@ int ATA_ReadDMA(Uint8 Disk, Uint64 Address, Uint Count, void *Buffer)
 	// Complete Transfer
 	ATA_int_BusMasterWriteByte( cont * 8, 8 );	// Read and stop
 
-	val = inb(base+0x7);
-	LOG("Status byte = 0x%02x, Controller Status = 0x%02x",
-		val, ATA_int_BusMasterReadByte(cont * 8 + 2));
+	#if DEBUG
+	{
+		Uint8	val = inb(base+0x7);
+		LOG("Status byte = 0x%02x, Controller Status = 0x%02x",
+			val, ATA_int_BusMasterReadByte(cont * 8 + 2));
+	}
+	#else
+	inb(base+0x7);
+	#endif
 
 	if( gaATA_IRQs[cont] == 0 )
 	{