X-Git-Url: https://git.ucc.asn.au/?a=blobdiff_plain;f=Modules%2FUDI%2Finclude%2Fudi_physio.h;h=1397b1c05ae7ce95e09a197b3f5d229d704445b6;hb=b289025913a0e4573181155aeeaab37ed92cf525;hp=08b380ed15db81f9cf53f3c46a453f8cc19e32d3;hpb=72971b71efdb2cb7b7dbf7299e426320169d4e3e;p=tpg%2Facess2.git

diff --git a/Modules/UDI/include/udi_physio.h b/Modules/UDI/include/udi_physio.h
index 08b380ed..1397b1c0 100644
--- a/Modules/UDI/include/udi_physio.h
+++ b/Modules/UDI/include/udi_physio.h
@@ -1,26 +1,144 @@
 /**
+ * \file udi_physio.h
  */
 #ifndef _UDI_PHYSIO_H_
+#define _UDI_PHYSIO_H_
+
 #include <udi.h>
 
+// === TYPEDEFS ===
+// DMA Core
+typedef _udi_handle_t	udi_dma_handle_t;
+#define	UDI_NULL_DMA_HANDLE	_NULL_HANDLE
+typedef Uint64	udi_busaddr64_t;	//!< \note Opaque
+typedef struct udi_scgth_element_32_s	udi_scgth_element_32_t;
+typedef struct udi_scgth_element_64_s	udi_scgth_element_64_t;
+typedef struct udi_scgth_s	udi_scgth_t;
+typedef _udi_handle_t	udi_dma_constraints_t;
+#define UDI_NULL_DMA_CONSTRAINTS	_NULL_HANDLE
 /**
- * \name Bus Operations
+ * \name DMA constraints attributes
  * \{
  */
-typedef struct {
-	udi_cb_t	gcb;
-}	udi_bus_bind_cb_t;
-
+typedef udi_ubit8_t udi_dma_constraints_attr_t;
+/* DMA Convenience Attribute Codes */
+#define UDI_DMA_ADDRESSABLE_BITS          100
+#define UDI_DMA_ALIGNMENT_BITS            101
+/* DMA Constraints on the Entire Transfer */
+#define UDI_DMA_DATA_ADDRESSABLE_BITS     110
+#define UDI_DMA_NO_PARTIAL                111
+/* DMA Constraints on the Scatter/Gather  List */
+#define UDI_DMA_SCGTH_MAX_ELEMENTS        120
+#define UDI_DMA_SCGTH_FORMAT              121
+#define UDI_DMA_SCGTH_ENDIANNESS          122
+#define UDI_DMA_SCGTH_ADDRESSABLE_BITS    123
+#define UDI_DMA_SCGTH_MAX_SEGMENTS        124
+/* DMA Constraints on Scatter/Gather Segments */
+#define UDI_DMA_SCGTH_ALIGNMENT_BITS      130
+#define UDI_DMA_SCGTH_MAX_EL_PER_SEG      131
+#define UDI_DMA_SCGTH_PREFIX_BYTES        132
+/* DMA Constraints on Scatter/Gather Elements */
+#define UDI_DMA_ELEMENT_ALIGNMENT_BITS    140
+#define UDI_DMA_ELEMENT_LENGTH_BITS       141
+#define UDI_DMA_ELEMENT_GRANULARITY_BITS 142
+/* DMA Constraints for Special Addressing */
+#define UDI_DMA_ADDR_FIXED_BITS           150
+#define UDI_DMA_ADDR_FIXED_TYPE           151
+#define UDI_DMA_ADDR_FIXED_VALUE_LO       152
+#define UDI_DMA_ADDR_FIXED_VALUE_HI       153
+/* DMA Constraints on DMA Access Behavior */
+#define UDI_DMA_SEQUENTIAL                160
+#define UDI_DMA_SLOP_IN_BITS              161
+#define UDI_DMA_SLOP_OUT_BITS             162
+#define UDI_DMA_SLOP_OUT_EXTRA            163
+#define UDI_DMA_SLOP_BARRIER_BITS         164
+/* Values for UDI_DMA_SCGTH_ENDIANNESS */
+#define UDI_DMA_LITTLE_ENDIAN             (1U<<6)
+#define UDI_DMA_BIG_ENDIAN                (1U<<5)
+/* Values for UDI_DMA_ADDR_FIXED_TYPE */
+#define UDI_DMA_FIXED_ELEMENT             1
 /**
- * \brief Bus Bind Control Block Group Number
+ * \}
  */
-#define UDI_BUS_BIND_CB_NUM	1
+// DMA Constraints Management
+typedef struct udi_dma_constraints_attr_spec_s	udi_dma_constraints_attr_spec_t;
+typedef void udi_dma_constraints_attr_set_call_t(
+	udi_cb_t *gcb, udi_dma_constraints_t new_constraints, udi_status_t status
+	);
+typedef	struct udi_dma_limits_s	udi_dma_limits_t;
 
-extern void	udi_bus_bind_req(udi_bus_bind_cb_t *cb);
 
-extern void	udi_bus_unbind_req(udi_bus_bind_cb_t *cb);
-/**
- * \}
- */
+// === STRUCTURES ===
+// --- DMA Constraints Management ---
+struct udi_dma_constraints_attr_spec_s
+{
+     udi_dma_constraints_attr_t	attr_type;
+     udi_ubit32_t	attr_value;
+};
+// --- DMA Core ---
+struct udi_dma_limits_s
+{
+     udi_size_t max_legal_contig_alloc;
+     udi_size_t max_safe_contig_alloc;
+     udi_size_t cache_line_size;
+};
+struct udi_scgth_element_32_s
+{
+     udi_ubit32_t	block_busaddr;
+     udi_ubit32_t	block_length;
+};
+struct udi_scgth_element_64_s
+{
+     udi_busaddr64_t	block_busaddr;
+     udi_ubit32_t	block_length;
+     udi_ubit32_t	el_reserved;
+};
+/* Extension Flag */
+#define UDI_SCGTH_EXT                    0x80000000
+struct udi_scgth_s
+{
+     udi_ubit16_t	scgth_num_elements;
+     udi_ubit8_t	scgth_format;
+     udi_boolean_t	scgth_must_swap;
+     union {
+          udi_scgth_element_32_t	*el32p;
+          udi_scgth_element_64_t	*el64p;
+     }	scgth_elements;
+     union {
+          udi_scgth_element_32_t	el32;
+          udi_scgth_element_64_t	el64;
+     }	scgth_first_segment;
+};
+/* Values for scgth_format */
+#define UDI_SCGTH_32                     (1U<<0)
+#define UDI_SCGTH_64                     (1U<<1)
+#define UDI_SCGTH_DMA_MAPPED             (1U<<6)
+#define UDI_SCGTH_DRIVER_MAPPED          (1U<<7)
+
+
+
+// === FUNCTIONS ===
+// --- DMA Constraints Management ---
+extern void udi_dma_constraints_attr_set(
+	udi_dma_constraints_attr_set_call_t	*callback,
+	udi_cb_t	*gcb,
+	udi_dma_constraints_t	src_constraints,
+	const udi_dma_constraints_attr_spec_t	*attr_list,
+	udi_ubit16_t	list_length,
+	udi_ubit8_t	flags
+	);
+/* Constraints Flags */
+#define UDI_DMA_CONSTRAINTS_COPY (1U<<0)
+
+extern void udi_dma_constraints_attr_reset(
+	udi_dma_constraints_t	constraints,
+	udi_dma_constraints_attr_t	attr_type
+	);
+
+extern void udi_dma_constraints_free(udi_dma_constraints_t constraints);
+
+#include <physio/meta_intr.h>
+#include <physio/meta_bus.h>
+
 
 #endif