X-Git-Url: https://git.ucc.asn.au/?a=blobdiff_plain;f=ROM2%2Fcomm.h;fp=ROM2%2Fcomm.h;h=69f8d004e60faef59b04e55d2dca1f07d81b9f5d;hb=2e7a8beb908896930042bc0564fbd16f3e0b0b62;hp=0000000000000000000000000000000000000000;hpb=81ad17d2164523859d14464b9950a39f87e04937;p=uccvend-snackrom.git

diff --git a/ROM2/comm.h b/ROM2/comm.h
new file mode 100644
index 0000000..69f8d00
--- /dev/null
+++ b/ROM2/comm.h
@@ -0,0 +1,122 @@
+#ifndef _COMM_H_
+#define _COMM_H_
+
+#include "vend.h"
+
+/*
+ * The communications protocol:
+ *
+ * \n used for separating packets. Caps is important.
+ *
+ * Messages Sent:
+ *  KX - keypad press where X is (ascii 0..9 or R)
+ *  CXXXXX - coin balance, XXXXX is number of cents.
+ *  MXYY - dispense ack/nack. X is what happened (0..MOTOR_*_FAIL), YY is the motor
+ *
+ * Messages Received:
+ *  VXX - vend a slot XX
+ *  DXXXXXXXXXXX - write the string XXXXXXXXXX to screen (10 chars)
+ *  B - beep
+ *  U - query current coin balance. - replies with CXXXXX
+ *  GXXXXX - give change, XXXXX is the amount of the cost of the item hence change
+ *           is the current value in the coin mech - XXXXX
+ *
+ */
+
+#define TX_BUFFER_LEN 6 /* maximum 13 due to the way tx_int works with the FIFO */
+extern char tx_buffer[TX_BUFFER_LEN+2]; /* \n + null terminated */
+#define RX_BUFFER_LEN 11
+extern volatile char rx_buffer[RX_BUFFER_LEN+1]; /* null terminated */
+extern volatile char msg_buf[RX_BUFFER_LEN+1]; /* rx_buffer copied here w/o \n */
+
+/* rx_queue_state denotes the state of rx_buffer & msg_buf. Is one of:
+ *  0: both rx_buffer & msg_buf are empty and there are no msgs
+ *  1: msg_buf has a pending msg, but rx_buffer is not yet full.
+ *  2: msg_buf has a pending msg, as does rx_buffer - further msgs will be lost
+ */
+extern volatile u8 rx_queue_state;
+
+/* tx_queue_state bits are: 
+ *  bit 0: if the tx_buffer has a message pending to be sent.
+ *  bit 1: if the TX fifo is in use.
+ */
+extern volatile u8 tx_queue_state;
+
+void comm_init();
+void msg_clr();
+
+/*************************************/
+/*** 16550 UART specific #defines  ***/
+/*************************************/
+
+#define UART_SPEED 4915200 /* FIXME divide this by some magic number */
+#define BAUD_RATE  9600
+
+/* Register offsets for _uart_regs */
+	/* Must be accessed with DLAB low */
+#define UART_RX_BUFFER    0x00 /* read  */
+#define UART_TX_BUFFER    0x00 /* write */
+#define UART_INT_ENABLE   0x01
+#define UART_INT_IDENT    0x02 /* read  */
+#define UART_FIFO_CTL     0x02 /* write */
+#define UART_LINE_CTL     0x03
+#define UART_MODEM_CTL    0x04
+#define UART_LINE_STATUS  0x05
+#define UART_MODEM_STATUS 0x06
+#define UART_SCRATCH      0x07
+
+	/* Same addresses as above, but accessed with DLAB high */
+#define UART_DLAB_LSB     0x00
+#define UART_DLAB_MSB     0x01
+
+extern volatile u8 _uart_regs[]; /* UART registers - fixed at link time */
+
+/* The following #define's adapted from Minix 2.0.0's rs232.c */
+
+/* Interrupt enable bits. */
+#define IE_RECEIVER_READY       1
+#define IE_TRANSMITTER_READY    2
+#define IE_LINE_STATUS_CHANGE   4
+#define IE_MODEM_STATUS_CHANGE  8
+
+/* Interrupt status bits. */
+#define IS_MODEM_STATUS_CHANGE  0x00
+#define IS_TRANSMITTER_READY    0x02
+#define IS_RECEIVER_READY       0x04
+#define IS_LINE_STATUS_CHANGE   0x06
+#define IS_FIFO_TIMEOUT         0x0C
+
+/* FIFO control bits. */
+#define FIFO_ENABLE          0x01
+#define FIFO_RX_CLEAR        0x02
+#define FIFO_TX_CLEAR        0x04
+#define FIFO_DMA_ENABLE      0x08
+#define FIFO_LVL_1           (0x00<<6)
+#define FIFO_LVL_4           (0x01<<6)
+#define FIFO_LVL_8           (0x10<<6)
+#define FIFO_LVL_14          (0x11<<6)
+
+/* Line control bits. */
+#define LC_5BITS             0x00
+#define LC_6BITS             0x01
+#define LC_7BITS             0x10
+#define LC_8BITS             0x11
+#define LC_2STOP_BITS        0x04
+#define LC_PARITY            0x08
+#define LC_PAREVEN           0x10
+#define LC_BREAK             0x40
+#define LC_DLAB              0x80
+
+/* Line status bits. */
+#define LS_DATA_READY           1
+#define LS_OVERRUN_ERR          2
+#define LS_PARITY_ERR           4
+#define LS_FRAMING_ERR          8
+#define LS_BREAK_INTERRUPT   0x10
+#define LS_TRANSMITTER_READY 0x20
+
+/* Modem control bits. */
+#define MC_OUT1                 4
+#define MC_OUT2                 8
+
+#endif /* _COMM_H_ */