X-Git-Url: https://git.ucc.asn.au/?a=blobdiff_plain;f=UDI%2Fdrivers%2Fnet_ne2000%2Fne2000_core.c;h=d630a8d4abba32239321b2db36416dbbce5daf1b;hb=7e9bbefbdcbfdba27eb6cdacae0811f428483892;hp=11fc72f97cf02716e7f62268c0cf6d6db9dbd488;hpb=a80a1a7c3ee2c4eab8ee0038d3da9f3d9c2f2c48;p=tpg%2Facess2.git

diff --git a/UDI/drivers/net_ne2000/ne2000_core.c b/UDI/drivers/net_ne2000/ne2000_core.c
index 11fc72f9..d630a8d4 100644
--- a/UDI/drivers/net_ne2000/ne2000_core.c
+++ b/UDI/drivers/net_ne2000/ne2000_core.c
@@ -5,120 +5,40 @@
  * ne2000_core.c
  * - UDI initialisation 
  */
-#include <udi.h>
-#include <udi_nic.h>
 #include "ne2000_common.h"
 
-#define NE2K_META_BUS	1
-#define NE2K_META_NIC	2
+enum {
+	NE2K_META_BUS = 1,
+	NE2K_META_NIC,
+};
+enum {
+	NE2K_OPS_DEV = 1,
+	NE2K_OPS_CTRL,
+	NE2K_OPS_TX,
+	NE2K_OPS_RX,
+	NE2K_OPS_IRQ,
+};
+enum {
+	NE2K_CB_BUS_BIND = 1,
+	NE2K_CB_INTR,
+	NE2K_CB_INTR_EVENT,
+};
+
+#define NE2K_NUM_INTR_EVENT_CBS	4
 
 // === GLOBALS ===
-#define PIO_op_RI(op, reg, sz, val)	{UDI_PIO_##op+UDI_PIO_DIRECT+UDI_PIO_##reg, UDI_PIO_##sz##BYTE, val}
-#define PIO_MOV_RI1(reg, val)	PIO_op_RI(LOAD_IMM, reg, 1, val)
-#define PIO_OUT_RI1(reg, ofs)	PIO_op_RI(OUT, reg, 1, ofs)
-#define PIO_IN_RI1(reg, ofs)	PIO_op_RI(IN, reg, 1, ofs)
 // --- Programmed IO ---
-/// Ne2000 reset operation (reads MAC address too)
-udi_pio_trans_t	ne2k_pio_reset[] = {
-	// - Reset card
-	PIO_IN_RI1(R0, NE2K_REG_RESET),
-	PIO_OUT_RI1(R0, NE2K_REG_RESET),
-	// While ISR bit 7 is unset, spin
-	{UDI_PIO_LABEL, 0, 1},
-		PIO_IN_RI1(R0, NE2K_REG_ISR),
-		{UDI_PIO_AND_IMM+UDI_PIO_R0, UDI_PIO_1BYTE, 0x80},
-	{UDI_PIO_CSKIP+UDI_PIO_R0, UDI_PIO_1BYTE, UDI_PIO_NZ},
-	{UDI_PIO_BRANCH, 0, 1},
-	// ISR = 0x80 [Clear reset]
-	PIO_OUT_RI1(R0, NE2K_REG_ISR),
-	// - Init pass 1
-	// CMD = 0x40|0x21 [Page1, NoDMA, Stop]
-	PIO_MOV_RI1(R0, 0x40|0x21),
-	PIO_OUT_RI1(R0, NE2K_REG_CMD),
-	// CURR = First RX page
-	PIO_MOV_RI1(R0, NE2K_RX_FIRST_PG),
-	PIO_OUT_RI1(R0, NE2K_REG_CURR),
-	// CMD = 0x21 [Page0, NoDMA, Stop]
-	PIO_MOV_RI1(R0, 0x21),
-	PIO_OUT_RI1(R0, NE2K_REG_CMD),
-	// DCR = ? [WORD, ...]
-	PIO_MOV_RI1(R0, 0x49),
-	PIO_OUT_RI1(R0, NE2K_REG_DCR),
-	// IMR = 0 [Disable all]
-	PIO_MOV_RI1(R0, 0x00),
-	PIO_OUT_RI1(R0, NE2K_REG_IMR),
-	// ISR = 0xFF [ACK all]
-	PIO_MOV_RI1(R0, 0xFF),
-	PIO_OUT_RI1(R0, NE2K_REG_ISR),
-	// RCR = 0x20 [Monitor]
-	PIO_MOV_RI1(R0, 0x20),
-	PIO_OUT_RI1(R0, NE2K_REG_RCR),
-	// TCR = 0x02 [TX Off, Loopback]
-	PIO_MOV_RI1(R0, 0x02),
-	PIO_OUT_RI1(R0, NE2K_REG_TCR),
-	// - Read MAC address from EEPROM (24 bytes from 0)
-	PIO_MOV_RI1(R0, 0),
-	PIO_MOV_RI1(R1, 0),
-	PIO_OUT_RI1(R0, NE2K_REG_RSAR0),
-	PIO_OUT_RI1(R1, NE2K_REG_RSAR1),
-	PIO_MOV_RI1(R0, 6*4),
-	PIO_MOV_RI1(R1, 0),
-	PIO_OUT_RI1(R0, NE2K_REG_RBCR0),
-	PIO_OUT_RI1(R1, NE2K_REG_RBCR1),
-	// CMD = 0x0A [Start remote DMA]
-	PIO_MOV_RI1(R0, 0x0A),
-	PIO_OUT_RI1(R0, NE2K_REG_CMD),
-	// Read MAC address
-	PIO_MOV_RI1(R0, 0),	// - Buffer offset (incremented by 1 each iteration)
-	PIO_MOV_RI1(R1, NE2K_REG_MEM),	// - Reg offset (no increment)
-	PIO_MOV_RI1(R2, 6),	// - Six iterations
-	{UDI_PIO_REP_IN_IND, UDI_PIO_1BYTE,
-		UDI_PIO_REP_ARGS(UDI_PIO_BUF, UDI_PIO_R0, 1, UDI_PIO_R1, 0, UDI_PIO_R2)},
-	// - Setup
-	// PSTART = First RX page [Receive area start]
-	PIO_MOV_RI1(R0, NE2K_RX_FIRST_PG),
-	PIO_OUT_RI1(R0, NE2K_REG_PSTART),
-	// BNRY = Last RX page - 1 [???]
-	PIO_MOV_RI1(R0, NE2K_RX_LAST_PG-1),
-	PIO_OUT_RI1(R0, NE2K_REG_BNRY),
-	// PSTOP = Last RX page [???]
-	PIO_MOV_RI1(R0, NE2K_RX_LAST_PG),
-	PIO_OUT_RI1(R0, NE2K_REG_PSTOP),
-	// > Clear all interrupt and set mask
-	// ISR = 0xFF [ACK all]
-	PIO_MOV_RI1(R0, 0xFF),
-	PIO_OUT_RI1(R0, NE2K_REG_ISR),
-	// IMR = 0x3F []
-	PIO_MOV_RI1(R0, 0x3F),
-	PIO_OUT_RI1(R0, NE2K_REG_IMR),
-	// CMD = 0x22 [NoDMA, Start]
-	PIO_MOV_RI1(R0, 0x22),
-	PIO_OUT_RI1(R0, NE2K_REG_CMD),
-	// RCR = 0x0F [Wrap, Promisc]
-	PIO_MOV_RI1(R0, 0x0F),
-	PIO_OUT_RI1(R0, NE2K_REG_RCR),
-	// TCR = 0x00 [Normal]
-	PIO_MOV_RI1(R0, 0x00),
-	PIO_OUT_RI1(R0, NE2K_REG_TCR),
-	// TPSR = 0x40 [TX Start]
-	PIO_MOV_RI1(R0, 0x40),
-	PIO_OUT_RI1(R0, NE2K_REG_TPSR),
-	// End
-	{UDI_PIO_END_IMM, UDI_PIO_2BYTE, 0}
-};
-struct {
-	udi_pio_trans_t	*trans_list;
-	udi_ubit16_t	list_length;
-	udi_ubit16_t	pio_attributes;
-} ne2k_pio_ops[] = {
-	{ne2k_pio_reset, ARRAY_SIZEOF(ne2k_pio_reset), 0}
-};
-const int NE2K_NUM_PIO_OPS = ARRAY_SIZEOF(ne2k_pio_ops);
+#include "ne2000_pio.h"
 
 // === CODE ===
 // --- Management
 void ne2k_usage_ind(udi_usage_cb_t *cb, udi_ubit8_t resource_level)
 {
+	ne2k_rdata_t	*rdata = UDI_GCB(cb)->context;
+
+	rdata->rx_next_page = NE2K_RX_FIRST_PG;
+	
+	udi_usage_res(cb);
 }
 void ne2k_enumerate_req(udi_enumerate_cb_t *cb, udi_ubit8_t enumeration_level)
 {
@@ -134,15 +54,19 @@ void ne2k_enumerate_req(udi_enumerate_cb_t *cb, udi_ubit8_t enumeration_level)
 		attr_list ++;
 		DPT_SET_ATTR_STRING(attr_list, "if_media", "eth", 3);
 		attr_list ++;
-		NE2K_SET_ATTR_STRFMT(attr_list, "identifier", 2*6+1, "%2X%2X%2X%2X%2X%2X",
+		NE2K_SET_ATTR_STRFMT(attr_list, "identifier", 2*6+1, "%02X%02X%02X%02X%02X%02X",
 			rdata->macaddr[0], rdata->macaddr[1], rdata->macaddr[2],
 			rdata->macaddr[3], rdata->macaddr[4], rdata->macaddr[5] );
 		attr_list ++;
-		udi_enumerate_ack(cb, UDI_ENUMERATE_OK, 2);
+		cb->attr_valid_length = attr_list - cb->attr_list;
+		udi_enumerate_ack(cb, UDI_ENUMERATE_OK, NE2K_OPS_CTRL);
 		break;
 	case UDI_ENUMERATE_NEXT:
 		udi_enumerate_ack(cb, UDI_ENUMERATE_DONE, 0);
 		break;
+	default:
+		udi_assert(!"invalid enumeration_level");
+		break;
 	}
 }
 void ne2k_devmgmt_req(udi_mgmt_cb_t *cb, udi_ubit8_t mgmt_op, udi_ubit8_t parent_ID)
@@ -154,15 +78,22 @@ void ne2k_final_cleanup_req(udi_mgmt_cb_t *cb)
 // --- Bus
 void ne2k_bus_dev_channel_event_ind(udi_channel_event_cb_t *cb)
 {
+	udi_cb_t	*gcb = UDI_GCB(cb);
+	ne2k_rdata_t	*rdata = gcb->context;
+	
 	switch(cb->event)
 	{
 	case UDI_CHANNEL_CLOSED:
 		break;
 	case UDI_CHANNEL_BOUND: {
+		rdata->active_cb = gcb;
 		udi_bus_bind_cb_t *bus_bind_cb = UDI_MCB(cb->params.parent_bound.bind_cb, udi_bus_bind_cb_t);
 		udi_bus_bind_req( bus_bind_cb );
 		// continue at ne2k_bus_dev_bus_bind_ack
 		return; }
+	default:
+		udi_assert(!"invalid channel event");
+		break;
 	}
 }
 void ne2k_bus_dev_bus_bind_ack(udi_bus_bind_cb_t *cb,
@@ -179,9 +110,10 @@ void ne2k_bus_dev_bind__pio_map(udi_cb_t *gcb, udi_pio_handle_t new_pio_handle)
 {
 	ne2k_rdata_t	*rdata = gcb->context;
 	
-	if( rdata->init.pio_index != -1 )
+	if( rdata->init.pio_index != (udi_index_t)-1 )
 	{
 		rdata->pio_handles[rdata->init.pio_index] = new_pio_handle;
+		udi_debug_printf("PIO %i = %p\n", rdata->init.pio_index, new_pio_handle);
 	}
 	rdata->init.pio_index ++;
 	if( rdata->init.pio_index < NE2K_NUM_PIO_OPS )
@@ -192,17 +124,88 @@ void ne2k_bus_dev_bind__pio_map(udi_cb_t *gcb, udi_pio_handle_t new_pio_handle)
 			ne2k_pio_ops[rdata->init.pio_index].list_length,
 			UDI_PIO_LITTLE_ENDIAN, 0, 0
 			);
+		return ;
 	}
-	else
+	
+	// Next: Bind interrupt
+	// - spawn_idx = Interrupt number (0)
+	udi_channel_spawn(ne2k_bus_dev_bind__intr_chanel, gcb, gcb->channel,
+		0, NE2K_OPS_IRQ, rdata);
+	// V V V V
+}
+void ne2k_bus_dev_bind__intr_chanel(udi_cb_t *gcb, udi_channel_t new_channel)
+{
+	ne2k_rdata_t	*rdata = gcb->context;
+	
+	rdata->interrupt_channel = new_channel;
+	
+	udi_cb_alloc(ne2k_bus_dev_bind__intr_attach, gcb, NE2K_CB_INTR, gcb->channel);
+	// V V V V
+}
+void ne2k_bus_dev_bind__intr_attach(udi_cb_t *gcb, udi_cb_t *new_cb)
+{
+	ne2k_rdata_t	*rdata = gcb->context;
+	if( !new_cb )
 	{
-		// Next!
+		// Oh...
+		udi_channel_event_complete( UDI_MCB(rdata->active_cb, udi_channel_event_cb_t),
+			UDI_STAT_RESOURCE_UNAVAIL );
+		return ;
 	}
+	udi_intr_attach_cb_t	*intr_cb = UDI_MCB(new_cb, udi_intr_attach_cb_t);
+	intr_cb->interrupt_idx = 0;
+	intr_cb->min_event_pend = 2;
+	intr_cb->preprocessing_handle = rdata->pio_handles[NE2K_PIO_IRQACK];
+	udi_intr_attach_req(intr_cb);
+	// continued in ne2k_bus_dev_intr_attach_ack
 }
 void ne2k_bus_dev_bus_unbind_ack(udi_bus_bind_cb_t *cb)
 {
 }
 void ne2k_bus_dev_intr_attach_ack(udi_intr_attach_cb_t *intr_attach_cb, udi_status_t status)
 {
+	udi_cb_t	*gcb = UDI_GCB(intr_attach_cb);
+	ne2k_rdata_t	*rdata = gcb->context;
+	// continuing from ne2k_bus_dev_bind__intr_attach
+	if( status != UDI_OK ) {
+		// TODO: Error
+		udi_cb_free( UDI_GCB(intr_attach_cb) );
+		return ;
+	}
+	
+	rdata->intr_attach_cb = intr_attach_cb;
+	
+	rdata->init.n_intr_event_cb = 0;
+	udi_cb_alloc(ne2k_bus_dev_bind__intr_event_cb, gcb, NE2K_CB_INTR_EVENT, rdata->interrupt_channel);
+	// V V V V
+}
+void ne2k_bus_dev_bind__intr_event_cb(udi_cb_t *gcb, udi_cb_t *new_cb)
+{
+	ne2k_rdata_t	*rdata = gcb->context;
+	
+	udi_intr_event_cb_t *intr_event_cb = UDI_MCB(new_cb, udi_intr_event_cb_t);
+	udi_intr_event_rdy(intr_event_cb);
+	rdata->init.n_intr_event_cb ++;
+	
+	if( rdata->init.n_intr_event_cb < NE2K_NUM_INTR_EVENT_CBS )
+	{
+		udi_cb_alloc(ne2k_bus_dev_bind__intr_event_cb, gcb,
+			NE2K_CB_INTR_EVENT, rdata->interrupt_channel);
+		// A A A A
+		return ;
+	}
+
+	udi_pio_trans(ne2k_bus_dev_bind__card_reset, gcb,
+		rdata->pio_handles[NE2K_PIO_RESET], 0, NULL, &rdata->macaddr);
+	// V V V V
+}
+
+void ne2k_bus_dev_bind__card_reset(udi_cb_t *gcb, udi_buf_t *new_buf, udi_status_t status, udi_ubit16_t result)
+{	
+	ne2k_rdata_t	*rdata = gcb->context;
+	// Done! (Finally)
+	udi_channel_event_complete( UDI_MCB(rdata->active_cb, udi_channel_event_cb_t), UDI_OK );
+	// = = = =
 }
 void ne2k_bus_dev_intr_detach_ack(udi_intr_detach_cb_t *intr_detach_cb)
 {
@@ -213,12 +216,51 @@ void ne2k_nd_ctrl_channel_event_ind(udi_channel_event_cb_t *cb)
 }
 void ne2k_nd_ctrl_bind_req(udi_nic_bind_cb_t *cb, udi_index_t tx_chan_index, udi_index_t rx_chan_index)
 {
+	udi_cb_t	*gcb = UDI_GCB(cb);
+	ne2k_rdata_t	*rdata = gcb->context;
+	rdata->init.rx_chan_index = rx_chan_index;
+	udi_channel_spawn(ne2k_nd_ctrl_bind__tx_chan_ok, gcb, gcb->channel, tx_chan_index, NE2K_OPS_TX, rdata);
+	// V V V V
+}
+void ne2k_nd_ctrl_bind__tx_chan_ok(udi_cb_t *gcb, udi_channel_t new_channel)
+{
+	ne2k_rdata_t	*rdata = gcb->context;
+	rdata->tx_channel = new_channel;
+	udi_channel_spawn(ne2k_nd_ctrl_bind__rx_chan_ok, gcb, gcb->channel,
+		rdata->init.rx_chan_index, NE2K_OPS_RX, rdata);
+	// V V V V
+}
+void ne2k_nd_ctrl_bind__rx_chan_ok(udi_cb_t *gcb, udi_channel_t new_channel)
+{
+	ne2k_rdata_t	*rdata = gcb->context;
+	rdata->rx_channel = new_channel;
+	
+	udi_nic_bind_cb_t *cb = UDI_MCB(gcb, udi_nic_bind_cb_t);
+	cb->media_type = UDI_NIC_ETHER;
+	cb->min_pdu_size = 0;
+	cb->max_pdu_size = 0;
+	cb->rx_hw_threshold = 2;
+	cb->capabilities = 0;
+	cb->max_perfect_multicast = 0;
+	cb->max_total_multicast = 0;
+	cb->mac_addr_len = 6;
+	udi_memcpy(cb->mac_addr, rdata->macaddr, 6);
+	udi_nsr_bind_ack( cb, UDI_OK );
+	// = = = =
 }
 void ne2k_nd_ctrl_unbind_req(udi_nic_cb_t *cb)
 {
 }
 void ne2k_nd_ctrl_enable_req(udi_nic_cb_t *cb)
 {
+	udi_cb_t	*gcb = UDI_GCB(cb);
+	ne2k_rdata_t	*rdata = gcb->context;
+	udi_pio_trans(ne2k_nd_ctrl_enable_req__trans_done, gcb,
+		rdata->pio_handles[NE2K_PIO_ENABLE], 0, NULL, NULL);
+}
+void ne2k_nd_ctrl_enable_req__trans_done(udi_cb_t *gcb, udi_buf_t *new_buf, udi_status_t status, udi_ubit16_t res)
+{
+	udi_nsr_enable_ack( UDI_MCB(gcb, udi_nic_cb_t), status );
 }
 void ne2k_nd_ctrl_disable_req(udi_nic_cb_t *cb)
 {
@@ -229,6 +271,25 @@ void ne2k_nd_ctrl_ctrl_req(udi_nic_ctrl_cb_t *cb)
 void ne2k_nd_ctrl_info_req(udi_nic_info_cb_t *cb, udi_boolean_t reset_statistics)
 {
 }
+// --- IRQ
+void ne2k_bus_irq_channel_event_ind(udi_channel_event_cb_t *cb)
+{
+}
+void ne2k_bus_irq_intr_event_ind(udi_intr_event_cb_t *cb, udi_ubit8_t flags)
+{
+	udi_debug_printf("ne2k_bus_irq_intr_event_ind: flags=%x, intr_result=%x\n",
+		flags, cb->intr_result);
+	if( cb->intr_result & 0x01 )
+	{
+		ne2k_intr__rx_ok( UDI_GCB(cb) );
+	}
+	if( cb->intr_result & 0x40 )
+	{
+		// ne2k_intr__rdma( UDI_GCB(cb) );
+	}
+	// TODO: TX IRQs
+	udi_intr_event_rdy(cb);
+}
 
 // === Definition structures ===
 udi_mgmt_ops_t	ne2k_mgmt_ops = {
@@ -267,6 +328,12 @@ udi_nd_rx_ops_t	ne2k_nd_rx_ops = {
 	ne2k_nd_rx_rx_rdy
 };
 udi_ubit8_t	ne2k_nd_rx_ops_flags[2] = {0};
+udi_intr_handler_ops_t	ne2k_bus_irq_ops = {
+	ne2k_bus_irq_channel_event_ind,
+	ne2k_bus_irq_intr_event_ind
+};
+udi_ubit8_t	ne2k_bus_irq_ops_flags[2] = {0};
+
 udi_primary_init_t	ne2k_pri_init = {
 	.mgmt_ops = &ne2k_mgmt_ops,
 	.mgmt_op_flags = ne2k_mgmt_op_flags,
@@ -278,32 +345,45 @@ udi_primary_init_t	ne2k_pri_init = {
 };
 udi_ops_init_t	ne2k_ops_list[] = {
 	{
-		1, NE2K_META_BUS, UDI_BUS_DEVICE_OPS_NUM,
+		NE2K_OPS_DEV, NE2K_META_BUS, UDI_BUS_DEVICE_OPS_NUM,
 		0,
 		(udi_ops_vector_t*)&ne2k_bus_dev_ops,
 		ne2k_bus_dev_ops_flags
 	},
 	{
-		2, NE2K_META_NIC, UDI_ND_CTRL_OPS_NUM,
+		NE2K_OPS_CTRL, NE2K_META_NIC, UDI_ND_CTRL_OPS_NUM,
 		0,
 		(udi_ops_vector_t*)&ne2k_nd_ctrl_ops,
 		ne2k_nd_ctrl_ops_flags
 	},
 	{
-		3, NE2K_META_NIC, UDI_ND_TX_OPS_NUM,
+		NE2K_OPS_TX, NE2K_META_NIC, UDI_ND_TX_OPS_NUM,
 		0,
 		(udi_ops_vector_t*)&ne2k_nd_tx_ops,
 		ne2k_nd_tx_ops_flags
 	},
 	{
-		4, NE2K_META_NIC, UDI_ND_RX_OPS_NUM,
+		NE2K_OPS_RX, NE2K_META_NIC, UDI_ND_RX_OPS_NUM,
 		0,
 		(udi_ops_vector_t*)&ne2k_nd_rx_ops,
 		ne2k_nd_rx_ops_flags
 	},
+	{
+		NE2K_OPS_IRQ, NE2K_META_BUS, UDI_BUS_INTR_HANDLER_OPS_NUM,
+		0,
+		(udi_ops_vector_t*)&ne2k_bus_irq_ops,
+		ne2k_bus_irq_ops_flags
+	},
+	{0}
+};
+udi_cb_init_t ne2k_cb_init_list[] = {
+	{NE2K_CB_BUS_BIND, NE2K_META_BUS, UDI_BUS_BIND_CB_NUM, 0, 0,NULL},
+	{NE2K_CB_INTR, NE2K_META_BUS, UDI_BUS_INTR_ATTACH_CB_NUM, 0, 0,NULL},
+	{NE2K_CB_INTR_EVENT, NE2K_META_BUS, UDI_BUS_INTR_EVENT_CB_NUM, 0, 0,NULL},
 	{0}
 };
 const udi_init_t	udi_init_info = {
 	.primary_init_info = &ne2k_pri_init,
-	.ops_init_list = ne2k_ops_list
+	.ops_init_list = ne2k_ops_list,
+	.cb_init_list = ne2k_cb_init_list,
 };