X-Git-Url: https://git.ucc.asn.au/?a=blobdiff_plain;f=src%2Ffpu.vhd;fp=src%2Ffpu.vhd;h=50a9531e34eb4dfd7826df4e7ab33e54a9f1abf5;hb=bf561f5566c6e50af09f078b0773fd4abaff6281;hp=71b88ab18fd505412d863158e6b9ec765205bbcc;hpb=ecbc325cc08fb2731d1fc820a87979b75b4306bc;p=ipdf%2Fvfpu.git diff --git a/src/fpu.vhd b/src/fpu.vhd index 71b88ab..50a9531 100644 --- a/src/fpu.vhd +++ b/src/fpu.vhd @@ -1,46 +1,6 @@ -------------------------------------------------------------------------------- --- --- Project: --- +------------------------------------------------------------------------------- -- Description: top entity -------------------------------------------------------------------------------- --- --- 100101011010011100100 --- 110000111011100100000 --- 100000111011000101101 --- 100010111100101111001 --- 110000111011101101001 --- 010000001011101001010 --- 110100111001001100001 --- 110111010000001100111 --- 110110111110001011101 --- 101110110010111101000 --- 100000010111000000000 --- --- Author: Jidan Al-eryani --- E-mail: jidan@gmx.net --- --- Copyright (C) 2006 --- --- This source file may be used and distributed without --- restriction provided that this copyright statement is not --- removed from the file and that any derivative work contains --- the original copyright notice and the associated disclaimer. --- --- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY --- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED --- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR --- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, --- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE --- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR --- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF --- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT --- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- +-- See COPYRIGHT.jop library ieee; @@ -122,55 +82,55 @@ architecture rtl of fpu is -- ***Add/Substract units signals*** - signal prenorm_addsub_fracta_28_o, prenorm_addsub_fractb_28_o : std_logic_vector(27 downto 0); - signal prenorm_addsub_exp_o : std_logic_vector(7 downto 0); + signal prenorm_addsub_fracta_28_o, prenorm_addsub_fractb_28_o : std_logic_vector(FRAC_COMP_WIDTH-1 downto 0); + signal prenorm_addsub_exp_o : std_logic_vector(EXP_WIDTH-1 downto 0); - signal addsub_fract_o : std_logic_vector(27 downto 0); + signal addsub_fract_o : std_logic_vector(FRAC_COMP_WIDTH-1 downto 0); signal addsub_sign_o : std_logic; - signal postnorm_addsub_output_o : std_logic_vector(31 downto 0); + signal postnorm_addsub_output_o : std_logic_vector(FP_WIDTH-1 downto 0); signal postnorm_addsub_ine_o : std_logic; -- ***Multiply units signals*** signal pre_norm_mul_exp_10 : std_logic_vector(9 downto 0); - signal pre_norm_mul_fracta_24 : std_logic_vector(23 downto 0); - signal pre_norm_mul_fractb_24 : std_logic_vector(23 downto 0); + signal pre_norm_mul_fracta_24 : std_logic_vector(FRAC_WIDTH downto 0); + signal pre_norm_mul_fractb_24 : std_logic_vector(FRAC_WIDTH downto 0); - signal mul_24_fract_48 : std_logic_vector(47 downto 0); + signal mul_24_fract_48 : std_logic_vector(2*FRAC_WIDTH+1 downto 0); signal mul_24_sign : std_logic; - signal serial_mul_fract_48 : std_logic_vector(47 downto 0); + signal serial_mul_fract_48 : std_logic_vector(2*FRAC_WIDTH+1 downto 0); signal serial_mul_sign : std_logic; - signal mul_fract_48: std_logic_vector(47 downto 0); + signal mul_fract_48: std_logic_vector(2*FRAC_WIDTH+1 downto 0); signal mul_sign: std_logic; - signal post_norm_mul_output : std_logic_vector(31 downto 0); + signal post_norm_mul_output : std_logic_vector(FP_WIDTH-1 downto 0); signal post_norm_mul_ine : std_logic; -- ***Division units signals*** signal pre_norm_div_dvdnd : std_logic_vector(49 downto 0); - signal pre_norm_div_dvsor : std_logic_vector(26 downto 0); + signal pre_norm_div_dvsor : std_logic_vector(FRAC_WIDTH+3 downto 0); signal pre_norm_div_exp : std_logic_vector(EXP_WIDTH+1 downto 0); - signal serial_div_qutnt : std_logic_vector(26 downto 0); - signal serial_div_rmndr : std_logic_vector(26 downto 0); + signal serial_div_qutnt : std_logic_vector(FRAC_WIDTH+3 downto 0); + signal serial_div_rmndr : std_logic_vector(FRAC_WIDTH+3 downto 0); signal serial_div_sign : std_logic; signal serial_div_div_zero : std_logic; - signal post_norm_div_output : std_logic_vector(31 downto 0); + signal post_norm_div_output : std_logic_vector(FP_WIDTH-1 downto 0); signal post_norm_div_ine : std_logic; -- ***Square units*** - signal pre_norm_sqrt_fracta_o : std_logic_vector(51 downto 0); + signal pre_norm_sqrt_fracta_o : std_logic_vector(2*(FRAC_COMP_WIDTH-2)-1 downto 0); signal pre_norm_sqrt_exp_o : std_logic_vector(7 downto 0); - signal sqrt_sqr_o : std_logic_vector(25 downto 0); + signal sqrt_sqr_o : std_logic_vector(FRAC_WIDTH+2 downto 0); signal sqrt_ine_o : std_logic; - signal post_norm_sqrt_output : std_logic_vector(31 downto 0); + signal post_norm_sqrt_output : std_logic_vector(FP_WIDTH-1 downto 0); signal post_norm_sqrt_ine_o : std_logic; @@ -192,8 +152,8 @@ begin fpu_op_i => s_fpu_op_i(0), fracta_i => prenorm_addsub_fracta_28_o, fractb_i => prenorm_addsub_fractb_28_o, - signa_i => s_opa_i(31), - signb_i => s_opb_i(31), + signa_i => s_opa_i(FP_WIDTH-1), + signb_i => s_opb_i(FP_WIDTH-1), fract_o => addsub_fract_o, sign_o => addsub_sign_o); @@ -227,8 +187,8 @@ begin clk_i => clk_i, fracta_i => pre_norm_mul_fracta_24, fractb_i => pre_norm_mul_fractb_24, - signa_i => s_opa_i(31), - signb_i => s_opb_i(31), + signa_i => s_opa_i(FP_WIDTH-1), + signb_i => s_opb_i(FP_WIDTH-1), start_i => start_i, fract_o => mul_24_fract_48, sign_o => mul_24_sign, @@ -239,8 +199,8 @@ begin clk_i => clk_i, fracta_i => pre_norm_mul_fracta_24, fractb_i => pre_norm_mul_fractb_24, - signa_i => s_opa_i(31), - signb_i => s_opb_i(31), + signa_i => s_opa_i(FP_WIDTH-1), + signb_i => s_opb_i(FP_WIDTH-1), start_i => s_start_i, fract_o => serial_mul_fract_48, sign_o => serial_mul_sign, @@ -279,8 +239,8 @@ begin clk_i=> clk_i, dvdnd_i => pre_norm_div_dvdnd, dvsor_i => pre_norm_div_dvsor, - sign_dvd_i => s_opa_i(31), - sign_div_i => s_opb_i(31), + sign_dvd_i => s_opa_i(FP_WIDTH-1), + sign_div_i => s_opb_i(FP_WIDTH-1), start_i => s_start_i, ready_o => open, qutnt_o => serial_div_qutnt, @@ -421,8 +381,8 @@ begin end process; - s_infa <= '1' when s_opa_i(30 downto 23)="11111111" else '0'; - s_infb <= '1' when s_opb_i(30 downto 23)="11111111" else '0'; + s_infa <= '1' when s_opa_i(FP_WIDTH-2 downto FRAC_WIDTH)= (FP_WIDTH-2 downto FRAC_WIDTH => '1') else '0'; + s_infb <= '1' when s_opb_i(FP_WIDTH-2 downto FRAC_WIDTH)= (FP_WIDTH-2 downto FRAC_WIDTH => '1') else '0'; --In round down: the subtraction of two equal numbers other than zero are always -0!!! @@ -430,18 +390,18 @@ begin begin if s_rmode_i="00" or (s_div_zero_o or (s_infa or s_infb) or s_qnan_o or s_snan_o)='1' then --round-to-nearest-even s_output_o <= s_output1; - elsif s_rmode_i="01" and s_output1(30 downto 23)="11111111" then + elsif s_rmode_i="01" and s_output1(FP_WIDTH-2 downto FRAC_WIDTH)="11111111" then --In round-to-zero: the sum of two non-infinity operands is never infinity,even if an overflow occures - s_output_o <= s_output1(31) & "1111111011111111111111111111111"; - elsif s_rmode_i="10" and s_output1(31 downto 23)="111111111" then + s_output_o <= s_output1(FP_WIDTH-1) & "1111111011111111111111111111111"; + elsif s_rmode_i="10" and s_output1(FP_WIDTH-1 downto FRAC_WIDTH)="111111111" then --In round-up: the sum of two non-infinity operands is never negative infinity,even if an overflow occures s_output_o <= "11111111011111111111111111111111"; elsif s_rmode_i="11" then --In round-down: a-a= -0 - if (s_fpu_op_i="000" or s_fpu_op_i="001") and s_zero_o='1' and (s_opa_i(31) or (s_fpu_op_i(0) xor s_opb_i(31)))='1' then - s_output_o <= "1" & s_output1(30 downto 0); + if (s_fpu_op_i="000" or s_fpu_op_i="001") and s_zero_o='1' and (s_opa_i(FP_WIDTH-1) or (s_fpu_op_i(0) xor s_opb_i(FP_WIDTH-1)))='1' then + s_output_o <= "1" & s_output1(FP_WIDTH-2 downto 0); --In round-down: the sum of two non-infinity operands is never postive infinity,even if an overflow occures - elsif s_output1(31 downto 23)="011111111" then + elsif s_output1(FP_WIDTH-1 downto FRAC_WIDTH)="011111111" then s_output_o <= "01111111011111111111111111111111"; else s_output_o <= s_output1; @@ -453,13 +413,13 @@ begin -- Generate Exceptions - s_underflow_o <= '1' when s_output1(30 downto 23)="00000000" and s_ine_o='1' else '0'; - s_overflow_o <= '1' when s_output1(30 downto 23)="11111111" and s_ine_o='1' else '0'; + s_underflow_o <= '1' when s_output1(FP_WIDTH-2 downto FRAC_WIDTH)="00000000" and s_ine_o='1' else '0'; + s_overflow_o <= '1' when s_output1(FP_WIDTH-2 downto FRAC_WIDTH)="11111111" and s_ine_o='1' else '0'; s_div_zero_o <= serial_div_div_zero when fpu_op_i="011" else '0'; - s_inf_o <= '1' when s_output1(30 downto 23)="11111111" and (s_qnan_o or s_snan_o)='0' else '0'; - s_zero_o <= '1' when or_reduce(s_output1(30 downto 0))='0' else '0'; - s_qnan_o <= '1' when s_output1(30 downto 0)=QNAN else '0'; - s_snan_o <= '1' when s_opa_i(30 downto 0)=SNAN or s_opb_i(30 downto 0)=SNAN else '0'; + s_inf_o <= '1' when s_output1(FP_WIDTH-2 downto FRAC_WIDTH)="11111111" and (s_qnan_o or s_snan_o)='0' else '0'; + s_zero_o <= '1' when or_reduce(s_output1(FP_WIDTH-2 downto 0))='0' else '0'; + s_qnan_o <= '1' when s_output1(FP_WIDTH-2 downto 0)=QNAN else '0'; + s_snan_o <= '1' when s_opa_i(FP_WIDTH-2 downto 0)=SNAN or s_opb_i(FP_WIDTH-2 downto 0)=SNAN else '0'; end rtl;