X-Git-Url: https://git.ucc.asn.au/?a=blobdiff_plain;f=src%2Fmain.vhd;fp=src%2Fmain.vhd;h=7e7521dfd0c6f582593f5ba1de4661f1a906f835;hb=bf561f5566c6e50af09f078b0773fd4abaff6281;hp=99596ee4650404121be12d5dbfc13fddb8f150bc;hpb=ecbc325cc08fb2731d1fc820a87979b75b4306bc;p=ipdf%2Fvfpu.git

diff --git a/src/main.vhd b/src/main.vhd
index 99596ee..7e7521d 100644
--- a/src/main.vhd
+++ b/src/main.vhd
@@ -10,6 +10,8 @@ use ieee.std_logic_misc.all;
 use std.textio.all;
 use work.txt_util.all;
 
+use work.fpupack.all;
+
         -- fpu operations (fpu_op_i):
 		-- ========================
 		-- 000 = add, 
@@ -55,18 +57,26 @@ component fpu
 	);   
 end component;
 
-
+-- Assigning default values doesn't seem to help the error messages :(
 signal clk_i : std_logic:= '1';
-signal opa_i, opb_i : std_logic_vector(31 downto 0) := (others => '0');
+signal opa_i, opb_i : std_logic_vector(FP_WIDTH-1 downto 0) := (others => '0');
 signal fpu_op_i		: std_logic_vector(2 downto 0) := (others => '0');
 signal rmode_i : std_logic_vector(1 downto 0) := (others => '0');
-signal output_o : std_logic_vector(31 downto 0) := (others => '0');
-signal start_i, ready_o : std_logic := '0';
-signal ine_o, overflow_o, underflow_o, div_zero_o, inf_o, zero_o, qnan_o, snan_o: std_logic := '0';
+signal output_o : std_logic_vector(FP_WIDTH-1 downto 0) := (others => '0');
+signal start_i : std_logic := '1';
+signal ready_o : std_logic := '1';
+signal ine_o : std_logic := '0';
+signal overflow_o : std_logic := '0';
+signal underflow_o : std_logic := '0';
+signal div_zero_o : std_logic := '0';
+signal inf_o : std_logic := '0';
+signal zero_o : std_logic := '0';
+signal qnan_o : std_logic := '0';
+signal snan_o : std_logic := '0';
 
 
 
-signal slv_out : std_logic_vector(31 downto 0);
+signal slv_out : std_logic_vector(FP_WIDTH-1 downto 0);
 
 constant CLK_PERIOD :time := 10 ns; -- period of clk period
 
@@ -104,7 +114,7 @@ begin
 		file input_file: TEXT open read_mode is "STD_INPUT"; 
 
 		variable file_line: line;
-		variable str_in: string(8 downto 1);
+		variable str_in: string(FP_WIDTH/4 downto 1);
 		variable str_fpu_op: string(3 downto 1);
 		variable str_rmode: string(2 downto 1);
 
@@ -112,6 +122,10 @@ begin
 
     begin
 		-- Read ops from input_file
+		--print(str(ZERO_VECTOR));
+		--print(str(INF));
+		--print(str(QNAN));
+		--print(str(SNAN));
 		start_i <= '0';
 		while not endfile(input_file) loop