X-Git-Url: https://git.ucc.asn.au/?a=blobdiff_plain;f=src%2Fmain.vhd;fp=src%2Fmain.vhd;h=99596ee4650404121be12d5dbfc13fddb8f150bc;hb=ecbc325cc08fb2731d1fc820a87979b75b4306bc;hp=0000000000000000000000000000000000000000;hpb=0e33e3a609436a1fd615c12592ea78b5a21f0385;p=ipdf%2Fvfpu.git

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+-- Simulates the fpu by reading signals from stdin and writing results to stdout
+-- See COPYRIGHT.jop for the original copyright notice.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.math_real.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_misc.all;
+use std.textio.all;
+use work.txt_util.all;
+
+        -- fpu operations (fpu_op_i):
+		-- ========================
+		-- 000 = add, 
+		-- 001 = substract, 
+		-- 010 = multiply, 
+		-- 011 = divide,
+		-- 100 = square root
+		-- 101 = unused
+		-- 110 = unused
+		-- 111 = unused
+		
+        -- Rounding Mode: 
+        -- ==============
+        -- 00 = round to nearest even(default), 
+        -- 01 = round to zero, 
+        -- 10 = round up, 
+        -- 11 = round down
+
+
+entity main is
+end main;
+
+architecture rtl of main is
+
+component fpu 
+    port (
+        clk_i       	: in std_logic;
+        opa_i       	: in std_logic_vector(31 downto 0);   
+        opb_i       	: in std_logic_vector(31 downto 0);
+        fpu_op_i		: in std_logic_vector(2 downto 0);
+        rmode_i 		: in std_logic_vector(1 downto 0);  
+        output_o    	: out std_logic_vector(31 downto 0);
+		ine_o 			: out std_logic;
+        overflow_o  	: out std_logic;
+        underflow_o 	: out std_logic;
+        div_zero_o  	: out std_logic;
+        inf_o			: out std_logic;
+        zero_o			: out std_logic;
+        qnan_o			: out std_logic;
+        snan_o			: out std_logic;
+        start_i	  		: in  std_logic;
+        ready_o 		: out std_logic	
+	);   
+end component;
+
+
+signal clk_i : std_logic:= '1';
+signal opa_i, opb_i : std_logic_vector(31 downto 0) := (others => '0');
+signal fpu_op_i		: std_logic_vector(2 downto 0) := (others => '0');
+signal rmode_i : std_logic_vector(1 downto 0) := (others => '0');
+signal output_o : std_logic_vector(31 downto 0) := (others => '0');
+signal start_i, ready_o : std_logic := '0';
+signal ine_o, overflow_o, underflow_o, div_zero_o, inf_o, zero_o, qnan_o, snan_o: std_logic := '0';
+
+
+
+signal slv_out : std_logic_vector(31 downto 0);
+
+constant CLK_PERIOD :time := 10 ns; -- period of clk period
+
+
+begin
+
+    -- instantiate fpu
+    i_fpu: fpu port map (
+			clk_i => clk_i,
+			opa_i => opa_i,
+			opb_i => opb_i,
+			fpu_op_i =>	fpu_op_i,
+			rmode_i => rmode_i,	
+			output_o => output_o,  
+			ine_o => ine_o,
+			overflow_o => overflow_o,
+			underflow_o => underflow_o,		
+        	div_zero_o => div_zero_o,
+        	inf_o => inf_o,
+        	zero_o => zero_o,		
+        	qnan_o => qnan_o, 		
+        	snan_o => snan_o,
+        	start_i => start_i,
+        	ready_o => ready_o);		
+			
+
+    ---------------------------------------------------------------------------
+    -- toggle clock
+    ---------------------------------------------------------------------------
+    clk_i <= not(clk_i) after 5 ns;
+
+
+    mainloop : process 
+		--The operands and results are in Hex format. 
+		file input_file: TEXT open read_mode is "STD_INPUT"; 
+
+		variable file_line: line;
+		variable str_in: string(8 downto 1);
+		variable str_fpu_op: string(3 downto 1);
+		variable str_rmode: string(2 downto 1);
+
+
+
+    begin
+		-- Read ops from input_file
+		start_i <= '0';
+		while not endfile(input_file) loop
+
+			wait for CLK_PERIOD; 
+			start_i <= '1';
+			
+			str_read(input,str_in);
+			opa_i <= strhex_to_slv(str_in);
+			
+			str_read(input,str_in);
+			opb_i <= strhex_to_slv(str_in);
+
+			str_read(input_file,str_fpu_op);
+			fpu_op_i <= to_std_logic_vector(str_fpu_op);
+			
+			str_read(input_file,str_rmode);
+			rmode_i <= to_std_logic_vector(str_rmode);
+			
+			str_read(input_file,str_in);
+			slv_out <= strhex_to_slv(str_in);
+
+			wait for CLK_PERIOD;
+			start_i <= '0'; 
+			wait until ready_o='1';
+			
+			
+			print(hstr(output_o));
+			
+		end loop;		
+    	wait;
+    end process mainloop;
+
+end rtl;