From: Sam Moore <matches@ucc.asn.au>
Date: Mon, 14 Apr 2014 15:20:41 +0000 (+0800)
Subject: Tidy File I/O in mainloop
X-Git-Url: https://git.ucc.asn.au/?a=commitdiff_plain;ds=sidebyside;h=e005897cffaf46cbbed14b3cc1ef74a390c93fef;hp=e005897cffaf46cbbed14b3cc1ef74a390c93fef;p=ipdf%2Fvfpu.git

Tidy File I/O in mainloop

I tried really hard to do binary file I/O but failed.

Guess how VHDL represents a file of "bits"?
As an ASCII text file of "0" or "1" (!)

So looks like ASCII string -> hex -> std_logic_vector is best we can do.
I guess what people don't know won't hurt them... much.

Fixed some mistakes, mainloop was still trying to read the comparison output, also I called the file "input_file"
and there was a variable called "input" still that was getting read -_-
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