From: John Hodge Date: Wed, 8 Feb 2012 06:59:58 +0000 (+0800) Subject: Merge branch 'master' of git://git.ucc.asn.au/tpg/acess2 X-Git-Tag: rel0.15~789 X-Git-Url: https://git.ucc.asn.au/?a=commitdiff_plain;h=51ab5f489bc356940c95cc936fd0508e8f07ea97;hp=5e32640df489bbd3066ce78cac5fd4c11366286d;p=tpg%2Facess2.git Merge branch 'master' of git://git.ucc.asn.au/tpg/acess2 --- diff --git a/KernelLand/Kernel/arch/armv7/mm_virt.c b/KernelLand/Kernel/arch/armv7/mm_virt.c index 460b334f..90655b63 100644 --- a/KernelLand/Kernel/arch/armv7/mm_virt.c +++ b/KernelLand/Kernel/arch/armv7/mm_virt.c @@ -37,7 +37,7 @@ typedef struct #define FRACTAL(table1, addr) ((table1)[ (0xFF8/4*1024) + ((addr)>>22)]) #define USRFRACTAL(addr) (*((Uint32*)(0x7FDFF000) + ((addr)>>22))) #define TLBIALL() __asm__ __volatile__ ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)) -#define TLBIMVA(addr) __asm__ __volatile__ ("mcr p15, 0, %0, c8, c7, 1;dsb;isb" : : "r" ((addr)&~0xFFF):"memory") +#define TLBIMVA(addr) __asm__ __volatile__ ("mcr p15, 0, %0, c8, c7, 1;dsb;isb" : : "r" (((addr)&~0xFFF)|1):"memory") #define DCCMVAC(addr) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((addr)&~0xFFF)) // === PROTOTYPES === @@ -166,8 +166,8 @@ int MM_int_SetPageInfo(tVAddr VAddr, tMM_PageInfo *pi) *desc = 0; TLBIMVA( VAddr ); DCCMVAC( (tVAddr) desc ); - #warning "HACK: TLBIALL" - TLBIALL(); +// #warning "HACK: TLBIALL" +// TLBIALL(); LEAVE('i', 0); return 0; } @@ -179,8 +179,8 @@ int MM_int_SetPageInfo(tVAddr VAddr, tMM_PageInfo *pi) *desc |= (pi->AP & 3) << 4; // AP *desc |= ((pi->AP >> 2) & 1) << 9; // APX TLBIMVA( VAddr ); - #warning "HACK: TLBIALL" - TLBIALL(); +// #warning "HACK: TLBIALL" +// TLBIALL(); DCCMVAC( (tVAddr) desc ); LEAVE('i', 0); return 0; diff --git a/KernelLand/Kernel/arch/armv7/proc.S b/KernelLand/Kernel/arch/armv7/proc.S index 531de299..8711dee6 100644 --- a/KernelLand/Kernel/arch/armv7/proc.S +++ b/KernelLand/Kernel/arch/armv7/proc.S @@ -46,8 +46,8 @@ SwitchTask: ldr r1, [sp,#4*10] tst r1, r1 mcrne p15, 0, r1, c2, c0, 0 @ Set TTBR0 to r0 - mov r1, #0 - mcrne p15, 0, r1, c8, c7, 0 @ TLBIALL - Invalidate all +# mov r1, #1 + mcrne p15, 0, r1, c8, c7, 0 @ TLBIALL - Invalid user space @ Restore SP mov sp, r0 diff --git a/KernelLand/Kernel/arch/armv7/start.S b/KernelLand/Kernel/arch/armv7/start.S index 8d9f3e4d..113c8a43 100644 --- a/KernelLand/Kernel/arch/armv7/start.S +++ b/KernelLand/Kernel/arch/armv7/start.S @@ -45,12 +45,11 @@ _start: mrc p15, 0, r0, c1, c0, 0 orr r0, r0, #1 orr r0, r0, #1 << 23 - mvn r1, #1 << 2 - and r0, r0, r1 mcr p15, 0, r0, c1, c0, 0 - @ HACK! Disable caching - mrc p15, 0, r1, c1, c0, 0 + @ HACK: Set ASID to non zero + mov r0, #1 + MCR p15,0,r0,c13,c0,1 ldr r2, =0xF1000000 mov r1, #'s' diff --git a/KernelLand/Kernel/drv/vterm.c b/KernelLand/Kernel/drv/vterm.c index 2ae38ee8..71c4d4a8 100644 --- a/KernelLand/Kernel/drv/vterm.c +++ b/KernelLand/Kernel/drv/vterm.c @@ -40,7 +40,7 @@ Uint64 VT_Write(tVFS_Node *Node, Uint64 Offset, Uint64 Length, const void *Buffe // === CONSTANTS === // === GLOBALS === -MODULE_DEFINE(0, VERSION, VTerm, VT_Install, NULL, DEFAULT_INPUT, NULL); +MODULE_DEFINE(0, VERSION, VTerm, VT_Install, NULL, NULL); tVFS_NodeType gVT_RootNodeType = { .TypeName = "VTerm Root", .ReadDir = VT_ReadDir, @@ -136,6 +136,9 @@ int VT_Install(char **Arguments) if(!gsVT_InputDevice) gsVT_InputDevice = (char*)DEFAULT_INPUT; else if( Module_EnsureLoaded( gsVT_InputDevice ) ) gsVT_InputDevice = (char*)DEFAULT_INPUT; + if( Module_EnsureLoaded( gsVT_OutputDevice ) ) { + Log_Error("VTerm", "Fallback input '%s' is not avaliable, input will not be avaliable", DEFAULT_INPUT); + } // Create device paths { diff --git a/KernelLand/Modules/Display/Tegra2Vid/main.c b/KernelLand/Modules/Display/Tegra2Vid/main.c index d9405be0..72ac697b 100644 --- a/KernelLand/Modules/Display/Tegra2Vid/main.c +++ b/KernelLand/Modules/Display/Tegra2Vid/main.c @@ -66,6 +66,7 @@ tVideo_IOCtl_Pos gTegra2Vid_CursorPos; */ int Tegra2Vid_Install(char **Arguments) { + return MODULE_ERR_NOTNEEDED; // KeyVal_Parse(&gTegra2Vid_KeyValueParser, Arguments); gpTegra2Vid_IOMem = (void*)MM_MapHWPages(gTegra2Vid_PhysBase, 256/4); @@ -94,7 +95,15 @@ int Tegra2Vid_Install(char **Arguments) Log_Debug("Tegra2Vid", "[0x%03x] = 0x%08x", i, gpTegra2Vid_IOMem[i]); } // return 1; - + + // HACK!!! +// { +// int w = 1980, h = 1080; +// gpTegra2Vid_IOMem[DC_DISP_DISP_ACTIVE_0] = (h << 16) | w; +// gpTegra2Vid_IOMem[DC_WIN_A_SIZE_0] = (h << 16) | w; +// gpTegra2Vid_IOMem[DC_WIN_A_PRESCALED_SIZE_0] = (h << 16) | w; +// } + giTegra2Vid_FramebufferSize = (gpTegra2Vid_IOMem[DC_WIN_A_SIZE_0]&0xFFFF) *(gpTegra2Vid_IOMem[DC_WIN_A_SIZE_0]>>16)*4; @@ -104,7 +113,15 @@ int Tegra2Vid_Install(char **Arguments) gpTegra2Vid_IOMem[DC_WINBUF_A_START_ADDR_0], (giTegra2Vid_FramebufferSize+PAGE_SIZE-1)/PAGE_SIZE ); - memset(gpTegra2Vid_Framebuffer, 0x1F, 0x1000); + memset(gpTegra2Vid_Framebuffer, 0xFF, 0x1000); + + gpTegra2Vid_IOMem[DC_WIN_A_WIN_OPTIONS_0] &= ~0x40; + gpTegra2Vid_IOMem[DC_WIN_A_COLOR_DEPTH_0] = 12; // Could be 13 (BGR/RGB) + gTegra2Vid_DrvUtil_BufInfo.Width = 1024; + gTegra2Vid_DrvUtil_BufInfo.Height = 768; + gTegra2Vid_DrvUtil_BufInfo.Pitch = 1024*4; + gTegra2Vid_DrvUtil_BufInfo.Depth = 32; + gTegra2Vid_DrvUtil_BufInfo.Framebuffer = gpTegra2Vid_Framebuffer; // Tegra2Vid_int_SetMode(4); @@ -288,10 +305,10 @@ int Tegra2Vid_int_SetMode(int Mode) *(Uint32*)(gpTegra2Vid_IOMem + DC_DISP_DISP_ACTIVE_0) = (mode->H << 16) | mode->W; *(Uint32*)(gpTegra2Vid_IOMem + DC_WIN_A_POSITION_0) = 0; - *(Uint32*)(gpTegra2Vid_IOMem + DC_WIN_A_SIZE_0) = (mode->H << 16) | mode->W; + *(Uint32*)(gpTegra2Vid_IOMem + DC_WIN_A_SIZE_0) = (h << 16) | w; *(Uint32*)(gpTegra2Vid_IOMem + DC_DISP_DISP_COLOR_CONTROL_0) = 0x8; // BASE888 *(Uint32*)(gpTegra2Vid_IOMem + DC_WIN_A_COLOR_DEPTH_0) = 12; // Could be 13 (BGR/RGB) - *(Uint32*)(gpTegra2Vid_IOMem + DC_WIN_A_PRESCALED_SIZE_0) = (mode->H << 16) | mode->W; + *(Uint32*)(gpTegra2Vid_IOMem + DC_WIN_A_PRESCALED_SIZE_0) = (h << 16) | w; Log_Debug("Tegra2Vid", "Mode %i (%ix%i) selected", Mode, w, h); diff --git a/KernelLand/Modules/Display/Tegra2Vid/tegra2.h b/KernelLand/Modules/Display/Tegra2Vid/tegra2.h index a3f126b6..c36b05e7 100644 --- a/KernelLand/Modules/Display/Tegra2Vid/tegra2.h +++ b/KernelLand/Modules/Display/Tegra2Vid/tegra2.h @@ -18,17 +18,51 @@ const struct sTegra2_Disp_Mode Uint16 HBP, VBP; } caTegra2Vid_Modes[] = { // TODO: VESA timings - {720, 487, 16,33, 63, 33, 59, 133}, // NTSC 2 - {720, 576, 12,33, 63, 33, 69, 193}, // PAL 2 (VFP shown as 2/33, used 33) - {720, 483, 16, 6, 63, 6, 59, 30}, // 480p - {1280, 720, 70, 5, 804, 6, 220, 20}, // 720p - {1920,1080, 44, 4, 884, 5, 148, 36}, // 1080p +// {720, 487, 16,33, 63, 33, 59, 133}, // NTSC 2 +// {720, 576, 12,33, 63, 33, 69, 193}, // PAL 2 (VFP shown as 2/33, used 33) +// {720, 483, 16, 6, 63, 6, 59, 30}, // 480p +// {1280, 720, 70, 5, 804, 6, 220, 20}, // 720p +// {1920,1080, 44, 4, 884, 5, 148, 36}, // 1080p // TODO: Can all but HA/VA be constant and those select the resolution? }; const int ciTegra2Vid_ModeCount = sizeof(caTegra2Vid_Modes)/sizeof(caTegra2Vid_Modes[0]); enum eTegra2_Disp_Regs { + DC_CMD_STATE_CONTROL_0 = 0x041, + DC_CMD_DISPLAY_WINDOW_HEADER_0, // 042 + DC_CMD_REG_ACT_CONTROL_0, // 043 + + DC_COM_CRC_CONTROL_0 = 0x300, + DC_COM_CRC_CHECKSUM_0, // 301 + DC_COM_PIN_OUTPUT_ENABLE0_0, // 302 + DC_COM_PIN_OUTPUT_ENABLE1_0, // 303 + DC_COM_PIN_OUTPUT_ENABLE2_0, // 304 + DC_COM_PIN_OUTPUT_ENABLE3_0, // 305 + DC_COM_PIN_OUTPUT_POLARITY0_0, // 306 + DC_COM_PIN_OUTPUT_POLARITY1_0, // 307 + DC_COM_PIN_OUTPUT_POLARITY2_0, // 308 + DC_COM_PIN_OUTPUT_POLARITY3_0, // 309 + DC_COM_PIN_OUTPUT_DATA0_0, // 30A + DC_COM_PIN_OUTPUT_DATA1_0, // 30B + DC_COM_PIN_OUTPUT_DATA2_0, // 30C + DC_COM_PIN_OUTPUT_DATA3_0, // 30D + DC_COM_PIN_INPUT_ENABLE0_0, // 30E + DC_COM_PIN_INPUT_ENABLE1_0, // 30F + DC_COM_PIN_INPUT_ENABLE2_0, // 310 + DC_COM_PIN_INPUT_ENABLE3_0, // 311 + DC_COM_PIN_INPUT_DATA0_0, // 312 + DC_COM_PIN_INPUT_DATA1_0, // 313 + DC_COM_PIN_OUTPUT_SELECT0_0, // 314 + DC_COM_PIN_OUTPUT_SELECT1_0, // 315 + DC_COM_PIN_OUTPUT_SELECT2_0, // 316 + DC_COM_PIN_OUTPUT_SELECT3_0, // 317 + DC_COM_PIN_OUTPUT_SELECT4_0, // 318 + DC_COM_PIN_OUTPUT_SELECT5_0, // 319 + DC_COM_PIN_OUTPUT_SELECT6_0, // 31A + DC_COM_PIN_MISC_CONTROL_0, // 31B + // TODO: Complete + DC_DISP_DISP_SIGNAL_OPTIONS0_0 = 0x400, DC_DISP_DISP_SIGNAL_OPTIONS1_0, // 401 DC_DISP_DISP_WIN_OPTIONS_0, // 402 @@ -40,11 +74,76 @@ enum eTegra2_Disp_Regs DC_DISP_BACK_PORCH_0, // 408 (TrimSlice 0x0004 003A) DC_DISP_DISP_ACTIVE_0, // 409 (TrimSlice 0x0300 0400) DC_DISP_FRONT_PORCH_0, // 40A (TrimSlice 0x0004 003A) - DC_DISP_H_PULSE0_CONTROL_0, // 40B + DC_DISP_H_PULSE0_POSITION_A_0, // 40C + DC_DISP_H_PULSE0_POSITION_B_0, // 40D + DC_DISP_H_PULSE0_POSITION_C_0, // 40E + DC_DISP_H_PULSE0_POSITION_D_0, // 40F + DC_DISP_H_PULSE1_CONTROL_0, // 410 + DC_DISP_H_PULSE1_POSITION_A_0, // 411 + DC_DISP_H_PULSE1_POSITION_B_0, // 412 + DC_DISP_H_PULSE1_POSITION_C_0, // 413 + DC_DISP_H_PULSE1_POSITION_D_0, // 414 + DC_DISP_H_PULSE2_CONTROL_0, // 415 + DC_DISP_H_PULSE2_POSITION_A_0, // 416 + DC_DISP_H_PULSE2_POSITION_B_0, // 417 + DC_DISP_H_PULSE2_POSITION_C_0, // 418 + DC_DISP_H_PULSE2_POSITION_D_0, // 419 + DC_DISP_V_PULSE0_CONTROL_0, // 41A + DC_DISP_V_PULSE0_POSITION_A_0, // 41B + DC_DISP_V_PULSE0_POSITION_B_0, // 41C + DC_DISP_V_PULSE0_POSITION_C_0, // 41D + DC_DISP_V_PULSE1_CONTROL_0, // 41E + DC_DISP_V_PULSE1_POSITION_A_0, // 41F + DC_DISP_V_PULSE1_POSITION_B_0, // 420 + DC_DISP_V_PULSE1_POSITION_C_0, // 421 + DC_DISP_V_PULSE2_CONTROL_0, // 422 + DC_DISP_V_PULSE2_POSITION_A_0, // 423 + DC_DISP_V_PULSE3_CONTROL_0, // 424 + DC_DISP_V_PULSE3_POSITION_A_0, // 425 + DC_DISP_M0_CONTROL_0, // 426 + DC_DISP_M1_CONTROL_0, // 427 + DC_DISP_DI_CONTROL_0, // 428 + DC_DISP_PP_CONTROL_0, // 429 + DC_DISP_PP_SELECT_A_0, // 42A + DC_DISP_PP_SELECT_B_0, // 42B + DC_DISP_PP_SELECT_C_0, // 42C + DC_DISP_PP_SELECT_D_0, // 42D + DC_DISP_DISP_CLOCK_CONTROL_0, // 42E + DC_DISP_DISP_INTERFACE_CONTROL_0,//42F + DC_DISP_DISP_COLOR_CONTROL_0, // 430 + DC_DISP_SHIFT_CLOCK_OPTIONS_0, // 431 + DC_DISP_DATA_ENABLE_OPTIONS_0, // 432 + DC_DISP_SERIAL_INTERFACE_OPTIONS_0, // 433 + DC_DISP_LCD_SPI_OPTIONS_0, // 434 + DC_DISP_BORDER_COLOR_0, // 435 + DC_DISP_COLOR_KEY0_LOWER_0, // 436 + DC_DISP_COLOR_KEY0_UPPER_0, // 437 + DC_DISP_COLOR_KEY1_LOWER_0, // 438 + DC_DISP_COLOR_KEY1_UPPER_0, // 439 + _DC_DISP_UNUSED_43A, + _DC_DISP_UNUSED_43B, + DC_DISP_CURSOR_FOREGROUND_0, // 43C - IMPORTANT + DC_DISP_CURSOR_BACKGROUND_0, // 43D - IMPORTANT + DC_DISP_CURSOR_START_ADDR_0, // 43E - IMPORTANT + DC_DISP_CURSOR_START_ADDR_NS_0, // 43F - IMPORTANT + DC_DISP_CURSOR_POSITION_0, // 440 - IMPORTANT + DC_DISP_CURSOR_POSITION_NS_0, // 441 - IMPORTANT + DC_DISP_INIT_SEQ_CONTROL_0, // 442 + DC_DISP_SPI_INIT_SEQ_DATA_A_0, // 443 + DC_DISP_SPI_INIT_SEQ_DATA_B_0, // 444 + DC_DISP_SPI_INIT_SEQ_DATA_C_0, // 445 + DC_DISP_SPI_INIT_SEQ_DATA_D_0, // 446 + + DC_DISP_DC_MCCIF_FIFOCTRL_0 = 0x480, + DC_DISP_MCCIF_DISPLAY0A_HYST_0, // 481 + DC_DISP_MCCIF_DISPLAY0B_HYST_0, // 482 + DC_DISP_MCCIF_DISPLAY0C_HYST_0, // 483 + DC_DISP_MCCIF_DISPLAY1B_HYST_0, // 484 + + DC_DISP_DAC_CRT_CTRL_0 = 0x4C0, + DC_DISP_DISP_MISC_CONTROL_0, // 4C1 - DC_DISP_DISP_COLOR_CONTROL_0 = 0x430, - DC_WINC_A_COLOR_PALETTE_0 = 0x500, DC_WINC_A_PALETTE_COLOR_EXT_0 = 0x600, DC_WIN_A_WIN_OPTIONS_0 = 0x700, diff --git a/KernelLand/Modules/Input/PS2KbMouse/pl050.c b/KernelLand/Modules/Input/PS2KbMouse/pl050.c index 839c0bda..a8dd0743 100644 --- a/KernelLand/Modules/Input/PS2KbMouse/pl050.c +++ b/KernelLand/Modules/Input/PS2KbMouse/pl050.c @@ -70,8 +70,8 @@ void PL050_EnableMouse(void) //PL050_WriteMouseData(0xD4); //PL050_WriteMouseData(0xF6); // Set Default Settings - PL050_WriteMouseData(0xD4); - PL050_WriteMouseData(0xF4); // Enable Packets +// PL050_WriteMouseData(0xD4); +// PL050_WriteMouseData(0xF4); // Enable Packets LOG("Done"); }