From: John Hodge <tpg@ucc.asn.au>
Date: Thu, 8 Mar 2012 11:30:14 +0000 (+0800)
Subject: Modules/AHCI - Initial fiddling
X-Git-Tag: rel0.15~738
X-Git-Url: https://git.ucc.asn.au/?a=commitdiff_plain;h=d8257630a3e339fbd878fefaaad3e650be2aad88;p=tpg%2Facess2.git

Modules/AHCI - Initial fiddling
---

diff --git a/KernelLand/Modules/Storage/AHCI/ahci.c b/KernelLand/Modules/Storage/AHCI/ahci.c
new file mode 100644
index 00000000..7a94aa4e
--- /dev/null
+++ b/KernelLand/Modules/Storage/AHCI/ahci.c
@@ -0,0 +1,25 @@
+/*
+* Acess2 Kernel - AHCI Driver
+* - By John Hodge (thePowersGang)
+*
+* ahci.c
+*/
+#include <drv_pci.h>
+#include "ahci.h"
+
+// === CODE ====
+int AHCI_Install(char **Arguments)
+{
+	// 010601/FFFFFF
+	while( (id = PCI_GetDeviceByClass(0x010000, 0xFF0000, id)) >= 0 && i < MAX_CONTROLLERS )
+	{
+		ctrlr->PMemBase = PCI_GetBAR(id, 5);
+		if( !ctrlr->PMemBase )
+		{
+			// TODO: Allocate space
+		}
+		
+		ctrlr->IRQNum = PCI_GetIRQ(id);
+	}
+	return 0;
+}
diff --git a/KernelLand/Modules/Storage/AHCI/ahci.h b/KernelLand/Modules/Storage/AHCI/ahci.h
new file mode 100644
index 00000000..cfed404c
--- /dev/null
+++ b/KernelLand/Modules/Storage/AHCI/ahci.h
@@ -0,0 +1,55 @@
+/*
+ * Acess2 Kernel - AHCI Driver
+ * - By John Hodge (thePowersGang)
+ *
+ * ahci.h
+ * - Driver header
+ */
+#ifndef _AHCI__AHCI_H_
+#define _AHCI__AHCI_H_
+
+#define AHCI_CAP_S64A	(1 << 31)	// Supports 64-bit addressing
+#define AHCI_CAP_SNCQ	(1 << 30)	// Supports Native Command Queuing
+#define AHCI_CAP_SXS	(1 << 5)	// Support External SATA
+
+struct sAHCI_MemSpace
+{
+	Uint32	CAP;	// Host Capabilities
+	Uint32	GHC;	// Global Host Control;
+	Uint16	IS;	// Interrupt Status
+	Uint16	PI;	// Ports Implemented
+	Uint32	VS;	// Version
+	Uint32	CCC_CTL;	// Command Completion Coalsecing Control
+	Uint16	CCC_PORTS;	// Command Completion Coalsecing Ports
+	Uint32	EM_LOC;	// Enclosure Management Location
+	Uint32	CAP2;	// Host Capabilities Extended
+	Uint16	BOHC;	// BIOS/OS Handoff Control and Status
+	
+	Uint16	_padding[(0x100-0x2C)/2];
+
+	struct s_port
+	{
+		Uint32	PxCLB;	// Command List Base Address
+		Uint32	PxCLBU;	// (High of above)
+		Uint32	PxFB;	// FIS Base Address
+		Uint32	PxFBU;	// (high of above)
+		Uint32	PxIS;	// Interrupt Status
+		Uint32	PxIE;	// Interrupt Enable
+		Uint32	PxCMD;	// Command and Status
+		Uint32	_resvd;
+		Uint32	PxTFD;	// Task File Data
+		Uint32	PxSIG;	// Signature
+		Uint32	PxSSTS;	// Serial ATA Status
+		Uint32	PxSCTL;	// Serial ATA Control
+		Uint32	PxSERR;	// Serial ATA Error
+		Uint32	PxSACT;	// Serial ATA Active
+		Uint32	PxCI;	// Command Issue
+		Uint32	PxSNTF;	// Serial ATA Notification
+		Uint32	PxFBS;	// FIS-based Switching Control
+		Uint32	_resvd2[(0x70-0x44)/4];
+		Uint32	PxVS[4];
+	}	Ports[32];
+};
+
+#endif
+