X-Git-Url: https://git.ucc.asn.au/?p=ipdf%2Fdocuments.git;a=blobdiff_plain;f=papers.bib;h=0dec3ca5784660c5d2da9615f82fa7bced1aa64f;hp=7cea9c90b57081ecd1c7ef6580908fec18810a69;hb=4d1387ba0e70247be33b2058ce8a603712bbc615;hpb=c6ca9623378dc9e4517a041ca309a38f36de9e04

diff --git a/papers.bib b/papers.bib
index 7cea9c9..0dec3ca 100644
--- a/papers.bib
+++ b/papers.bib
@@ -333,7 +333,7 @@ Goldberg:1991:CSK:103162.103163,
 	title = "Infinite-precision Document Formats (Project Proposal)",
 	author = "David Gow",
 	year = "2014",
-	howpublished = "http://davidgow.net/stuff/ProjectProposal.pdf"
+	howpublished = "\url{http://davidgow.net/stuff/ProjectProposal.pdf}"
 }
 
 % Note the different title
@@ -341,7 +341,7 @@ Goldberg:1991:CSK:103162.103163,
 	title = "Infinite Precision Document Formats (Project Proposal)",
 	author = "Sam Moore",
 	year = "2014",
-	howpublished = "http://szmoore.net/ipdf/documents/ProjectProposalSam.pdf"
+	howpublished = "\url{http://szmoore.net/ipdf/documents/ProjectProposalSam.pdf}"
 }
 
 % The Fractal Nature of Bezier Curves
@@ -482,3 +482,49 @@ doi={10.1109/ARITH.1991.145549},}
   organization={IEEE}
 }
 
+%ghdl, the least shitty of the open source vhdl tools
+@misc{ghdl,
+	title = "GHDL Guide",
+	author = "Tristan Gingold",
+	year = "2007",
+	howpublished = "\url{http://ghdl.free.fr/ghdl/}"
+}
+
+% Look into as an alternative to using text files for FPU simulation?
+@misc{tang2000using,
+	title = "Using Binary Files in VHDL Test Benches",
+	author = "Stephen Tang",
+	year = "2000",
+	howpublished = "\url{http://www.ece.ualberta.ca/~elliott/ee552/studentAppNotes/2000_w/vhdl/BinaryFileTestbenching/binary.html}",
+	note = "Application Notes (webpage)"
+}
+
+% On the design of IEEE floating point adders
+% Has algorithms!
+@INPROCEEDINGS{seidal2001onthe,
+author={Seidel, P.-M. and Even, G.},
+booktitle={Computer Arithmetic, 2001. Proceedings. 15th IEEE Symposium on},
+title={On the design of fast IEEE floating-point adders},
+year={2001},
+month={},
+pages={184-194},
+keywords={adders;circuit optimisation;floating point arithmetic;logic design;IEEE rounding modes;IEEE standard;addition;approximate counting;borrow-save representation;clock periods;complement subtraction;compound adders;double precision;fast IEEE floating-point adder design;fast circuits;latches;latency;leading zeros;logic levels;normalized numbers;normalized rounded sum/difference;optimization techniques;rounding algorithm;sign-magnitude computation;subtraction;Adders;Algorithm design and analysis;Circuits;Clocks;Delay;Design optimization;Latches;Logic design;Partitioning algorithms;Pipelines},
+doi={10.1109/ARITH.2001.930118},
+ISSN={1063-6889},}
+
+
+@article{demmel1996basic,
+	title = "Basic Issues in Floating Point Arithmetic and Error Analysis",
+	author = "Jim Demmel",
+	journal = "U.C. Berkeley CS267",
+	note = "Lecture Notes",
+	howpublished = "\url{http://www.cs.berkeley.edu/~demmel/cs267/lecture21/lecture21.html}"
+}
+
+@misc{grfpu_dasia,
+	title = "GRFPU - High Performance IEEE- 7 5 4 Floating- Point Unit",
+	author = "Edvin Catovic",
+	howpublished = "\url{http://www.gaisler.com/doc/grfpu_dasia.pdf}"
+}
+
+