X-Git-Url: https://git.ucc.asn.au/?p=ipdf%2Fdocuments.git;a=blobdiff_plain;f=papers.bib;h=0dec3ca5784660c5d2da9615f82fa7bced1aa64f;hp=bbbe44ac6950f4df3c73bec2b5e36424c5d4ca1e;hb=b17539df71843a2d782fd789407e52b8414bb09f;hpb=9596379997730f1eb5ef57f86860ce4b4dfa1c18

diff --git a/papers.bib b/papers.bib
index bbbe44a..0dec3ca 100644
--- a/papers.bib
+++ b/papers.bib
@@ -499,6 +499,18 @@ doi={10.1109/ARITH.1991.145549},}
 	note = "Application Notes (webpage)"
 }
 
+% On the design of IEEE floating point adders
+% Has algorithms!
+@INPROCEEDINGS{seidal2001onthe,
+author={Seidel, P.-M. and Even, G.},
+booktitle={Computer Arithmetic, 2001. Proceedings. 15th IEEE Symposium on},
+title={On the design of fast IEEE floating-point adders},
+year={2001},
+month={},
+pages={184-194},
+keywords={adders;circuit optimisation;floating point arithmetic;logic design;IEEE rounding modes;IEEE standard;addition;approximate counting;borrow-save representation;clock periods;complement subtraction;compound adders;double precision;fast IEEE floating-point adder design;fast circuits;latches;latency;leading zeros;logic levels;normalized numbers;normalized rounded sum/difference;optimization techniques;rounding algorithm;sign-magnitude computation;subtraction;Adders;Algorithm design and analysis;Circuits;Clocks;Delay;Design optimization;Latches;Logic design;Partitioning algorithms;Pipelines},
+doi={10.1109/ARITH.2001.930118},
+ISSN={1063-6889},}
 
 
 @article{demmel1996basic,