From: Sam Moore <matches@ucc.asn.au>
Date: Mon, 14 Apr 2014 15:20:41 +0000 (+0800)
Subject: Tidy File I/O in mainloop
X-Git-Url: https://git.ucc.asn.au/?p=ipdf%2Fvfpu.git;a=commitdiff_plain;h=e005897cffaf46cbbed14b3cc1ef74a390c93fef

Tidy File I/O in mainloop

I tried really hard to do binary file I/O but failed.

Guess how VHDL represents a file of "bits"?
As an ASCII text file of "0" or "1" (!)

So looks like ASCII string -> hex -> std_logic_vector is best we can do.
I guess what people don't know won't hurt them... much.

Fixed some mistakes, mainloop was still trying to read the comparison output, also I called the file "input_file"
and there was a variable called "input" still that was getting read -_-
---

diff --git a/src/main.vhd b/src/main.vhd
index 7e7521d..1ecc1c8 100644
--- a/src/main.vhd
+++ b/src/main.vhd
@@ -132,26 +132,31 @@ begin
 			wait for CLK_PERIOD; 
 			start_i <= '1';
 			
-			str_read(input,str_in);
+			str_read(input_file,str_in);
 			opa_i <= strhex_to_slv(str_in);
 			
-			str_read(input,str_in);
+			str_read(input_file,str_in);
 			opb_i <= strhex_to_slv(str_in);
 
 			str_read(input_file,str_fpu_op);
-			fpu_op_i <= to_std_logic_vector(str_fpu_op);
+			fpu_op_i <= strhex_to_slv(str_fpu_op)(2 downto 0);
 			
 			str_read(input_file,str_rmode);
-			rmode_i <= to_std_logic_vector(str_rmode);
-			
-			str_read(input_file,str_in);
-			slv_out <= strhex_to_slv(str_in);
+			rmode_i <= strhex_to_slv(str_rmode)(1 downto 0);
+
+
 
 			wait for CLK_PERIOD;
 			start_i <= '0'; 
 			wait until ready_o='1';
 			
+			--print("OpA"); print(hstr(opa_i));
+			--print("OpB"); print(hstr(opb_i));
+			--print("Opcode"); print(hstr(fpu_op_i));
+			print("Rmode"); print(hstr(rmode_i));
 			
+
+
 			print(hstr(output_o));
 			
 		end loop;