From: John Hodge <tpg@ucc.asn.au>
Date: Mon, 6 Feb 2012 06:20:20 +0000 (+0800)
Subject: Merge branch 'master' of git://git.ucc.asn.au/tpg/acess2
X-Git-Tag: rel0.15~792
X-Git-Url: https://git.ucc.asn.au/?p=tpg%2Facess2.git;a=commitdiff_plain;h=bfacdd3b71576cf6ceaa83352d3a7d162adb75e1;hp=30dd821bb12d4b815546fbd3561b3325fc80e5a7

Merge branch 'master' of git://git.ucc.asn.au/tpg/acess2

Conflicts:
	Kernel/drv/vterm.c
---

diff --git a/Kernel/arch/armv7/mm_virt.c b/Kernel/arch/armv7/mm_virt.c
index 460b334f..90655b63 100644
--- a/Kernel/arch/armv7/mm_virt.c
+++ b/Kernel/arch/armv7/mm_virt.c
@@ -37,7 +37,7 @@ typedef struct
 #define FRACTAL(table1, addr)	((table1)[ (0xFF8/4*1024) + ((addr)>>22)])
 #define USRFRACTAL(addr)	(*((Uint32*)(0x7FDFF000) + ((addr)>>22)))
 #define TLBIALL()	__asm__ __volatile__ ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0))
-#define TLBIMVA(addr)	__asm__ __volatile__ ("mcr p15, 0, %0, c8, c7, 1;dsb;isb" : : "r" ((addr)&~0xFFF):"memory")
+#define TLBIMVA(addr)	__asm__ __volatile__ ("mcr p15, 0, %0, c8, c7, 1;dsb;isb" : : "r" (((addr)&~0xFFF)|1):"memory")
 #define DCCMVAC(addr)	__asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((addr)&~0xFFF))
 
 // === PROTOTYPES ===
@@ -166,8 +166,8 @@ int MM_int_SetPageInfo(tVAddr VAddr, tMM_PageInfo *pi)
 				*desc = 0;
 				TLBIMVA( VAddr );
 				DCCMVAC( (tVAddr) desc );
-				#warning "HACK: TLBIALL"
-				TLBIALL();
+//				#warning "HACK: TLBIALL"
+//				TLBIALL();				
 				LEAVE('i', 0);
 				return 0;
 			}
@@ -179,8 +179,8 @@ int MM_int_SetPageInfo(tVAddr VAddr, tMM_PageInfo *pi)
 			*desc |= (pi->AP & 3) << 4;	// AP
 			*desc |= ((pi->AP >> 2) & 1) << 9;	// APX
 			TLBIMVA( VAddr );	
-			#warning "HACK: TLBIALL"
-			TLBIALL();
+//			#warning "HACK: TLBIALL"
+//			TLBIALL();
 			DCCMVAC( (tVAddr) desc );
 			LEAVE('i', 0);
 			return 0;
diff --git a/Kernel/arch/armv7/proc.S b/Kernel/arch/armv7/proc.S
index 531de299..8711dee6 100644
--- a/Kernel/arch/armv7/proc.S
+++ b/Kernel/arch/armv7/proc.S
@@ -46,8 +46,8 @@ SwitchTask:
 	ldr r1, [sp,#4*10]
 	tst r1, r1
 	mcrne p15, 0, r1, c2, c0, 0	@ Set TTBR0 to r0
-	mov r1, #0
-	mcrne p15, 0, r1, c8, c7, 0	@ TLBIALL - Invalidate all
+#	mov r1, #1
+	mcrne p15, 0, r1, c8, c7, 0	@ TLBIALL - Invalid user space
 
 	@ Restore SP
 	mov sp, r0
diff --git a/Kernel/arch/armv7/start.S b/Kernel/arch/armv7/start.S
index 8d9f3e4d..113c8a43 100644
--- a/Kernel/arch/armv7/start.S
+++ b/Kernel/arch/armv7/start.S
@@ -45,12 +45,11 @@ _start:
 	mrc p15, 0, r0, c1, c0, 0
 	orr r0, r0, #1
 	orr r0, r0, #1 << 23
-	mvn r1, #1 << 2
-	and r0, r0, r1
 	mcr p15, 0, r0, c1, c0, 0
 
-	@ HACK! Disable caching
-	mrc p15, 0, r1, c1, c0, 0
+	@ HACK: Set ASID to non zero
+	mov r0, #1
+	MCR p15,0,r0,c13,c0,1
 
 	ldr r2, =0xF1000000
 	mov r1, #'s'
diff --git a/Kernel/drv/vterm.c b/Kernel/drv/vterm.c
index 2ae38ee8..71c4d4a8 100644
--- a/Kernel/drv/vterm.c
+++ b/Kernel/drv/vterm.c
@@ -40,7 +40,7 @@ Uint64	VT_Write(tVFS_Node *Node, Uint64 Offset, Uint64 Length, const void *Buffe
 // === CONSTANTS ===
 
 // === GLOBALS ===
-MODULE_DEFINE(0, VERSION, VTerm, VT_Install, NULL, DEFAULT_INPUT, NULL);
+MODULE_DEFINE(0, VERSION, VTerm, VT_Install, NULL, NULL);
 tVFS_NodeType	gVT_RootNodeType = {
 	.TypeName = "VTerm Root",
 	.ReadDir = VT_ReadDir,
@@ -136,6 +136,9 @@ int VT_Install(char **Arguments)
 	
 	if(!gsVT_InputDevice)	gsVT_InputDevice = (char*)DEFAULT_INPUT;
 	else if( Module_EnsureLoaded( gsVT_InputDevice ) )	gsVT_InputDevice = (char*)DEFAULT_INPUT;
+	if( Module_EnsureLoaded( gsVT_OutputDevice ) ) {
+		Log_Error("VTerm", "Fallback input '%s' is not avaliable, input will not be avaliable", DEFAULT_INPUT);
+	}
 	
 	// Create device paths
 	{