Kernel/x86 - Added SSE/FPU state saving, not fully tested
[tpg/acess2.git] / Kernel / arch / x86 / include / mp.h
1 /*
2  */
3 #ifndef _MP_H
4 #define _MP_H
5
6 #define MPPTR_IDENT     ('_'|('M'<<8)|('P'<<16)|('_'<<24))
7 #define MPTABLE_IDENT   ('P'|('C'<<8)|('M'<<16)|('P'<<24))
8
9 typedef struct sMPInfo {
10         Uint32  Sig;    // '_MP_'
11         Uint32  MPConfig;
12         Uint8   Length;
13         Uint8   Version;
14         Uint8   Checksum;
15         Uint8   Features[5];    // 2-4 are unused
16 } tMPInfo;
17
18 typedef union uMPTable_Ent {
19         Uint8   Type;
20         struct {
21                 Uint8   Type;
22                 Uint8   APICID;
23                 Uint8   APICVer;
24                 Uint8   CPUFlags;       // bit 0: Enabled, bit 1: Boot Processor
25                 Uint32  CPUSignature;   // Stepping, Model, Family
26                 Uint32  FeatureFlags;
27                 Uint32  Reserved[2];
28         } __attribute__((packed))       Proc;   // 0x00
29         struct {
30                 Uint8   Type;
31                 Uint8   ID;
32                 char    TypeString[6];
33         } __attribute__((packed))       Bus;    // 0x01
34         struct {
35                 Uint8   Type;
36                 Uint8   ID;
37                 Uint8   Version;
38                 Uint8   Flags;  // bit 0: Enabled
39                 Uint32  Addr;
40         } __attribute__((packed))       IOAPIC; // 0x02
41         struct {
42                 Uint8   Type;
43                 Uint8   IntType;
44                 Uint16  Flags;  // 0,1: Polarity, 2,3: Trigger Mode
45                 Uint8   SourceBusID;
46                 Uint8   SourceBusIRQ;
47                 Uint8   DestAPICID;
48                 Uint8   DestAPICIRQ;
49         } __attribute__((packed))       IOInt;
50         struct {
51                 Uint8   Type;
52                 Uint8   IntType;
53                 Uint16  Flags;  // 0,1: Polarity, 2,3: Trigger Mode
54                 Uint8   SourceBusID;
55                 Uint8   SourceBusIRQ;
56                 Uint8   DestLocalAPICID;
57                 Uint8   DestLocalAPICIRQ;
58         } __attribute__((packed))       LocalInt;
59 } __attribute__((packed)) tMPTable_Ent;
60
61 typedef struct sMPTable {
62         Uint32  Sig;
63         Uint16  BaseTableLength;
64         Uint8   SpecRev;
65         Uint8   Checksum;
66         
67         char    OemID[8];
68         char    ProductID[12];
69         
70         Uint32  OEMTablePtr;
71         Uint16  OEMTableSize;
72         Uint16  EntryCount;
73         
74         Uint32  LocalAPICMemMap;        //!< Address used to access the local APIC
75         Uint16  ExtendedTableLen;
76         Uint8   ExtendedTableChecksum;
77         Uint8   Reserved;
78         
79         tMPTable_Ent    Entries[];
80 } tMPTable;
81
82 typedef volatile struct {
83         Uint32  Addr;
84         Uint32  Resvd1[3];
85         union {
86                 Uint8   Byte;
87                 Uint16  Word;
88                 Uint32  DWord;
89         }       Value;
90         Uint32  Resvd2[3];
91 }       tIOAPIC;
92
93 typedef struct {
94         Uint32  Val;
95         Uint32  Padding[3];
96 } volatile      tReg;
97
98 typedef volatile struct {
99         tReg    _unused1[2];
100         tReg    ID;
101         tReg    Version;
102         tReg    _unused2[4];
103         tReg    TPR;    // Task Priority Register
104         tReg    APR;    // Arbitration Priority Register (RO)
105         tReg    PPR;    // Processor Priority Register (RO)
106         tReg    EOI;    // EOI Register (Write Only)
107         tReg    _unused3[1];
108         tReg    LogDest;        // Logical Destination Register
109         tReg    DestFmt;        // Destination Format Register (0-27: RO, 28-31: RW)
110         tReg    SIV;    // Spurious Interrupt Vector Register (0-8: RW, 9-31: RO)
111         tReg    ISR[8]; // In-Service Register - Total 256 Bits (RO)
112         tReg    TMR[8]; // Trigger Mode Register - Total 256 Bits (RO)
113         tReg    IRR[8]; // Interrupt Request Register - Total 256 Bits (RO)
114         tReg    ErrorStatus;    // Error Status Register (RO)
115         tReg    _unused4[6];
116         tReg    LVTCMI; // LVT CMI Registers
117         // 0x300
118         tReg    ICR[2]; // Interrupt Command Register (RW)
119         // LVT Registers (Controls Local Vector Table)
120         // Structure:
121         // 0-7:   Vector - IDT Vector for the interrupt
122         // 12:    Delivery Status (0: Idle, 1: Send Pending)
123         // 16:    Mask (0: Enabled, 1: Disabled)
124         // 0x320
125         tReg    LVTTimer;       // LVT Timer Register (RW)
126         tReg    LVTThermalSensor;       // LVT Thermal Sensor Register (RW)
127         tReg    LVTPerfMonCounters;     // LVT Performance Monitor Counters Register (RW)
128         tReg    LVTLInt0;       // LVT Local Interrupt (LINT) #0 Register (RW);
129         tReg    LVTLInt1;       // LVT Local Interrupt (LINT) #1 Register (RW);
130         tReg    LVTError;       // LVT Error Register (RW);
131         // 0x380
132         tReg    InitialCount;   // Initial Count Register (Used for the timer) (RW)
133         tReg    CurrentCount;   // Current Count Register (Used for the timer) (RW)
134         tReg    _unused5[4];
135         // 0x3E0
136         tReg    DivideConifg;   // Divide Configuration Register (RW)
137         tReg    _unused6[1];
138 } volatile      tAPIC;
139
140 #endif

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