KernelLand/Kernel/arch/armv7/platform_tegra2.c

   1 /*
   2  * Acess2 Kernel ARMv7 Port
   3  * - By John Hodge (thePowersGang)
   4  *
   5  * platform_tegra2.c
   6  * - Tegra2 Core code
   7  */
   8 #include <acess.h>
   9 #include "platform_tegra2.h"
  10
  11 // === CONSTANTS ===
  12 #define TIMER0_INT      (0*32+0)        // Pri #0
  13 #define TIMER1_INT      (0*32+1)        // Pri #1
  14 #define TIMER2_INT      (1*32+9)        // Sec #9
  15 #define TIMER3_INT      (1*32+10)       // Sec #10
  16
  17 // === Imports ===
  18 extern volatile Sint64  giTimestamp;
  19 extern volatile Uint64  giTicks;
  20 extern volatile Uint64  giPartMiliseconds;
  21 extern void     Timer_CallTimers(void);
  22
  23 // === PROTORTYPES ===
  24 void    Timer_IRQHandler_SysClock(int IRQ, void *_unused);
  25 void    Time_Setup(void);
  26
  27 // === GLOBALS ===
  28 // - Addresses for the GIC to use
  29 tPAddr  gGIC_InterfaceAddr = 0x50040000;
  30 tPAddr  gGIC_DistributorAddr = 0x50041000;
  31 // - Map of timer registers
  32 volatile struct sTimersMap *gpTimersMap;
  33 volatile struct sClockResetMap *gpClockResetMap;
  34 // - Interrupt controller code commented out, because the Tegra2 also has a GIC
  35 #if 0
  36 struct sIRQMap  gpIRQMap;
  37 #endif
  38
  39 // === CODE ===
  40
  41 // -- Timers --
  42 void Timer_IRQHandler_SysClock(int IRQ, void *_unused)
  43 {
  44         giTimestamp += 100;
  45         gpTimersMap->TMR1.PCR_0 = (1<<30);
  46 }
  47
  48 void Time_Setup(void)
  49 {
  50         gpTimersMap = (void*)MM_MapHWPages(0x60005000, 1);
  51         gpClockResetMap = (void*)MM_MapHWPages(0x60006000, 1);
  52         // Timer 1 (used for system timekeeping)
  53         IRQ_AddHandler(0*32+0, Timer_IRQHandler_SysClock, NULL);
  54         gpTimersMap->TMR1.PTV_0 = (1<<31)|(1<<30)|(100*1000-1); // enable, periodic, 100 ms
  55         gpTimersMap->TMR1.PCR_0 = (1<<30);
  56         Log_Debug("Tegra2Tme", "TMR0.PCR = 0x%x", gpTimersMap->TMR1.PCR_0);
  57
  58         // Disabled until IRQs work
  59         //gpClockResetMap->RST_Source = (1 << 5)|(0<<4)|(7);    // Full reset on watchdog timeout
  60
  61         Log_Debug("Tegra2Tme", "TIMERUS_USEC_CFG = 0x%x", gpTimersMap->TIMERUS.USEC_CFG);
  62         Log_Debug("Tegra2Tme", "TIMERUS_CNTR_1US = 0x%x", gpTimersMap->TIMERUS.CNTR_1US);
  63         Log_Debug("Tegra2Tme", "TMR0.PCR = 0x%x", gpTimersMap->TMR1.PCR_0);
  64         Log_Debug("Tegra2Tme", "TMR0.PTV = 0x%x", gpTimersMap->TMR1.PTV_0);
  65         for( int i = 0; i < 5; i ++ ) {
  66                 for( int j = 0; j < 1000*1000; j ++ )
  67                 {
  68                         __asm__ __volatile__ ("mov r0, r0");
  69                         __asm__ __volatile__ ("mov r0, r0");
  70                         __asm__ __volatile__ ("mov r0, r0");
  71                 }
  72                 Log_Debug("Tegra2Tme", "TMR0.PCR = 0x%x", gpTimersMap->TMR1.PCR_0);
  73         }
  74         Log_Debug("Tegra2Tme", "TMR0.PCR = 0x%x", gpTimersMap->TMR1.PCR_0);
  75         Log_Debug("Tegra2Tme", "GICC_HPPIR = 0x%x", *(Uint32*)(0xF0000000 + 0x18));
  76         Log_Debug("Tegra2Tme", "GICC_IAR = 0x%x", *(Uint32*)(0xF0000000 + 0xC));
  77         Log_Debug("Tegra2Tme", "GICD_ISPENDR0 = 0x%x", *(Uint32*)(0xF0001000 + 0x200 + 0*4));
  78         Log_Debug("Tegra2Tme", "GICD_ISPENDR1 = 0x%x", *(Uint32*)(0xF0001000 + 0x200 + 1*4));
  79 }
  80
  81 #if 0
  82 // -- Interrupt Controller --
  83 void IRQ_CtrlrHandler(struct sIRQRegs *Ctrlr, int Ofs)
  84 {
  85         // Primary CPU only?
  86         // TODO:
  87 }
  88
  89 void IRQ_RootHandler(void)
  90 {
  91         IRQ_CtrlrHandler(&gpIRQMap->Pri, 0*32);
  92         IRQ_CtrlrHandler(&gpIRQMap->Sec, 1*32);
  93         IRQ_CtrlrHandler(&gpIRQMap->Tri, 2*32);
  94         IRQ_CtrlrHandler(&gpIRQMap->Quad, 3*32);
  95 }
  96
  97 void IRQ_Setup(void)
  98 {
  99         gpIRQMap = (void*)MM_MapHWPages(0x60004000, 1);
 100
 101         gpIRQHandler = IRQ_RootHandler;
 102 }
 103 #endif