3 * - By John Hodge (thePowersGang)
10 #include <udi_physio.h>
13 #include <drv_pci.h> // acess
14 #include <udi_internal.h>
15 #include <trans_pci.h>
18 /* Copied from http://projectudi.cvs.sourceforge.net/viewvc/projectudi/udiref/driver/udi_dpt/udi_dpt.h */
19 #define DPT_SET_ATTR_BOOLEAN(attr, name, val) \
20 udi_strcpy((attr)->attr_name, (name)); \
21 (attr)->attr_type = UDI_ATTR_BOOLEAN; \
22 (attr)->attr_length = sizeof(udi_boolean_t); \
23 UDI_ATTR32_SET((attr)->attr_value, (val))
25 #define DPT_SET_ATTR32(attr, name, val) \
26 udi_strcpy((attr)->attr_name, (name)); \
27 (attr)->attr_type = UDI_ATTR_UBIT32; \
28 (attr)->attr_length = sizeof(udi_ubit32_t); \
29 UDI_ATTR32_SET((attr)->attr_value, (val))
31 #define DPT_SET_ATTR_ARRAY8(attr, name, val, len) \
32 udi_strcpy((attr)->attr_name, (name)); \
33 (attr)->attr_type = UDI_ATTR_ARRAY8; \
34 (attr)->attr_length = (len); \
35 udi_memcpy((attr)->attr_value, (val), (len))
37 #define DPT_SET_ATTR_STRING(attr, name, val, len) \
38 udi_strcpy((attr)->attr_name, (name)); \
39 (attr)->attr_type = UDI_ATTR_STRING; \
40 (attr)->attr_length = (len); \
41 udi_strncpy_rtrim((char *)(attr)->attr_value, (val), (len))
43 #define PCI_OPS_BRIDGE 1
46 #define PCI_MAX_EVENT_CBS 8
51 udi_init_context_t init_context;
58 udi_child_chan_context_t child_chan_context;
60 udi_channel_t interrupt_channel;
69 udi_pio_handle_t intr_preprocessing;
70 udi_intr_event_cb_t *event_cbs[PCI_MAX_EVENT_CBS];
71 udi_index_t event_cb_wr_ofs;
72 udi_index_t event_cb_rd_ofs;
74 } pci_child_chan_context_t;
77 void pci_usage_ind(udi_usage_cb_t *cb, udi_ubit8_t resource_level);
78 void pci_enumerate_req(udi_enumerate_cb_t *cb, udi_ubit8_t enumeration_level);
79 void pci_devmgmt_req(udi_mgmt_cb_t *cb, udi_ubit8_t mgmt_op, udi_ubit8_t parent_ID);
80 void pci_final_cleanup_req(udi_mgmt_cb_t *cb);
82 void pci_bridge_ch_event_ind(udi_channel_event_cb_t *cb);
83 void pci_unbind_req(udi_bus_bind_cb_t *cb);
84 void pci_bind_req_op(udi_bus_bind_cb_t *cb);
85 void pci_intr_attach_req(udi_intr_attach_cb_t *cb);
86 void pci_intr_attach_req__channel_spawned(udi_cb_t *gcb, udi_channel_t new_channel);
87 void pci_intr_detach_req(udi_intr_detach_cb_t *cb);
89 void pci_intr_ch_event_ind(udi_channel_event_cb_t *cb);
90 void pci_intr_event_rdy(udi_intr_event_cb_t *cb);
91 void pci_intr_event_rdy__irqs_enabled(udi_cb_t *gcb, udi_buf_t *newbuf, udi_status_t status, udi_ubit16_t result);
92 void pci_intr_handler(int irq, void *void_context);
93 void pci_intr_handle__trans_done(udi_cb_t *gcb, udi_buf_t *new_buf, udi_status_t status, udi_ubit16_t result);
95 // - Hook to physio (UDI doesn't define these)
96 int pci_pio_get_regset(udi_cb_t *gcb, udi_ubit32_t regset_idx, void **baseptr, size_t *lenptr);
99 void pci_usage_ind(udi_usage_cb_t *cb, udi_ubit8_t resource_level)
101 pci_rdata_t *rdata = UDI_GCB(cb)->context;
109 switch(resource_level)
111 case UDI_RESOURCES_CRITICAL:
112 case UDI_RESOURCES_LOW:
113 case UDI_RESOURCES_NORMAL:
114 case UDI_RESOURCES_PLENTIFUL:
118 // TODO: Initialise rdata
119 rdata->cur_iter = -1;
123 void pci_enumerate_req(udi_enumerate_cb_t *cb, udi_ubit8_t enumeration_level)
125 pci_rdata_t *rdata = UDI_GCB(cb)->context;
126 switch(enumeration_level)
128 case UDI_ENUMERATE_START:
129 case UDI_ENUMERATE_START_RESCAN:
130 rdata->cur_iter = -1;
131 case UDI_ENUMERATE_NEXT:
133 if( (rdata->cur_iter = PCI_GetDeviceByClass(0,0, rdata->cur_iter)) == -1 )
135 udi_enumerate_ack(cb, UDI_ENUMERATE_DONE, 0);
139 udi_instance_attr_list_t *attr_list = cb->attr_list;
142 PCI_GetDeviceInfo(rdata->cur_iter, &ven, &dev, &class);
144 PCI_GetDeviceVersion(rdata->cur_iter, &revision);
146 PCI_GetDeviceSubsys(rdata->cur_iter, &sven, &sdev);
148 udi_strcpy(attr_list->attr_name, "identifier");
149 attr_list->attr_length = sprintf((char*)attr_list->attr_value,
150 "%04x%04x%02x%04x%04x",
151 ven, dev, revision, sven, sdev);
153 DPT_SET_ATTR_STRING(attr_list, "bus_type", "pci", 3);
155 DPT_SET_ATTR32(attr_list, "pci_vendor_id", ven);
157 DPT_SET_ATTR32(attr_list, "pci_device_id", dev);
160 cb->attr_valid_length = attr_list - cb->attr_list;
161 cb->child_ID = rdata->cur_iter;
162 udi_enumerate_ack(cb, UDI_ENUMERATE_OK, 1);
167 void pci_devmgmt_req(udi_mgmt_cb_t *cb, udi_ubit8_t mgmt_op, udi_ubit8_t parent_ID)
171 void pci_final_cleanup_req(udi_mgmt_cb_t *cb)
176 void pci_bridge_ch_event_ind(udi_channel_event_cb_t *cb)
180 void pci_bind_req(udi_bus_bind_cb_t *cb)
182 // TODO: "Lock" PCI device
184 // TODO: DMA constraints
185 udi_bus_bind_ack(cb, 0, UDI_DMA_LITTLE_ENDIAN, UDI_OK);
187 void pci_unbind_req(udi_bus_bind_cb_t *cb)
191 void pci_intr_attach_req(udi_intr_attach_cb_t *cb)
193 pci_child_chan_context_t *context = UDI_GCB(cb)->context;
195 ASSERT(cb->interrupt_idx == 0);
197 context->intr_preprocessing = cb->preprocessing_handle;
198 // Check if interrupt is already bound
199 if( !UDI_HANDLE_IS_NULL(context->interrupt_channel, udi_channel_t) )
201 udi_intr_attach_ack(cb, UDI_OK);
205 udi_channel_spawn(pci_intr_attach_req__channel_spawned, UDI_GCB(cb),
206 cb->gcb.channel, cb->interrupt_idx, PCI_OPS_IRQ, context);
208 void pci_intr_attach_req__channel_spawned(udi_cb_t *gcb, udi_channel_t new_channel)
210 udi_intr_attach_cb_t *cb = UDI_MCB(gcb, udi_intr_attach_cb_t);
211 pci_child_chan_context_t *context = UDI_GCB(cb)->context;
213 if( UDI_HANDLE_IS_NULL(new_channel, udi_channel_t) )
219 context->interrupt_channel = new_channel;
221 context->interrupt_handle = IRQ_AddHandler(
222 PCI_GetIRQ(context->child_chan_context.child_ID),
223 pci_intr_handler, context);
225 udi_intr_attach_ack(cb, UDI_OK);
227 void pci_intr_detach_req(udi_intr_detach_cb_t *cb)
232 void pci_intr_ch_event_ind(udi_channel_event_cb_t *cb)
236 void pci_intr_event_rdy(udi_intr_event_cb_t *cb)
238 pci_child_chan_context_t *context = UDI_GCB(cb)->context;
240 ASSERTC(context->event_cb_rd_ofs, <, PCI_MAX_EVENT_CBS);
241 ASSERTC(context->event_cb_wr_ofs, <, PCI_MAX_EVENT_CBS);
243 LOG("Rd %i, Wr %i [WR %p]", context->event_cb_rd_ofs, context->event_cb_wr_ofs, cb);
244 if( context->event_cbs[context->event_cb_wr_ofs] )
249 context->event_cbs[context->event_cb_wr_ofs++] = cb;
250 if( context->event_cb_wr_ofs == PCI_MAX_EVENT_CBS )
251 context->event_cb_wr_ofs = 0;
253 // TODO: Fire once >= min_event_pend CBs are recieved
254 if( !context->bIntrEnabled )
256 context->bIntrEnabled = 1;
257 udi_pio_trans(pci_intr_event_rdy__irqs_enabled, NULL, context->intr_preprocessing, 0, NULL, NULL);
260 void pci_intr_event_rdy__irqs_enabled(udi_cb_t *gcb, udi_buf_t *newbuf, udi_status_t status, udi_ubit16_t result)
265 void pci_intr_handler(int irq, void *void_context)
267 pci_child_chan_context_t *context = void_context;
269 LOG("irq=%i, context=%p", irq, context);
271 if( context->event_cb_rd_ofs == context->event_cb_wr_ofs ) {
276 ASSERTC(context->event_cb_rd_ofs, <, PCI_MAX_EVENT_CBS);
277 ASSERTC(context->event_cb_wr_ofs, <, PCI_MAX_EVENT_CBS);
279 udi_intr_event_cb_t *cb = context->event_cbs[context->event_cb_rd_ofs];
280 LOG("Rd %i, Wr %i [RD %p]", context->event_cb_rd_ofs, context->event_cb_wr_ofs, cb);
281 context->event_cbs[context->event_cb_rd_ofs] = NULL;
282 context->event_cb_rd_ofs ++;
283 if( context->event_cb_rd_ofs == PCI_MAX_EVENT_CBS )
284 context->event_cb_rd_ofs = 0;
287 if( UDI_HANDLE_IS_NULL(context->intr_preprocessing, udi_pio_handle_t) )
289 udi_intr_event_ind(cb, 0);
294 // - no event info, so mem_ptr=NULL
295 udi_pio_trans(pci_intr_handle__trans_done, UDI_GCB(cb),
296 context->intr_preprocessing, 1, cb->event_buf, NULL);
300 void pci_intr_handle__trans_done(udi_cb_t *gcb, udi_buf_t *new_buf, udi_status_t status, udi_ubit16_t result)
302 udi_intr_event_cb_t *cb = UDI_MCB(gcb, udi_intr_event_cb_t);
304 cb->intr_result = result;
306 udi_intr_event_ind(cb, UDI_INTR_PREPROCESSED);
310 udi_status_t pci_pio_do_io(uint32_t child_ID, udi_ubit32_t regset_idx, udi_ubit32_t ofs, udi_ubit8_t len,
311 void *data, bool isOutput)
313 // LOG("child_ID=%i, regset_idx=%i,ofs=0x%x,len=%i,data=%p,isOutput=%b",
314 // child_ID, regset_idx, ofs, len, data, isOutput);
315 tPCIDev pciid = child_ID;
316 // TODO: Cache child mappings
320 case UDI_PCI_CONFIG_SPACE:
322 return UDI_STAT_NOT_SUPPORTED;
323 case UDI_PCI_BAR_0 ... UDI_PCI_BAR_5: {
324 Uint32 bar = PCI_GetBAR(pciid, regset_idx);
329 #define _IO(fc, type) do {\
331 /*LOG("out"#fc"(0x%x, 0x%x)",bar+ofs,*(type*)data);*/\
332 out##fc(bar+ofs, *(type*)data); \
335 *(type*)data = in##fc(bar+ofs); \
336 /*LOG("in"#fc"(0x%x) = 0x%x",bar+ofs,*(type*)data);*/\
341 case UDI_PIO_1BYTE: _IO(b, udi_ubit8_t); return UDI_OK;
342 case UDI_PIO_2BYTE: _IO(w, udi_ubit16_t); return UDI_OK;
343 case UDI_PIO_4BYTE: _IO(d, udi_ubit32_t); return UDI_OK;
344 //case UDI_PIO_8BYTE: _IO(q, uint64_t); return UDI_OK;
346 return UDI_STAT_NOT_SUPPORTED;
353 //Uint64 longbar = PCI_GetValidBAR(pciid, regset_idx, PCI_BARTYPE_MEM);
354 return UDI_STAT_NOT_SUPPORTED;
358 return UDI_STAT_NOT_UNDERSTOOD;
362 // === UDI Functions ===
363 udi_mgmt_ops_t pci_mgmt_ops = {
367 pci_final_cleanup_req
369 udi_ubit8_t pci_mgmt_op_flags[4] = {0,0,0,0};
370 udi_bus_bridge_ops_t pci_bridge_ops = {
371 pci_bridge_ch_event_ind,
377 udi_ubit8_t pci_bridge_op_flags[5] = {0,0,0,0,0};
378 udi_intr_dispatcher_ops_t pci_irq_ops = {
379 pci_intr_ch_event_ind,
382 udi_ubit8_t pci_irq_ops_flags[2] = {0,0};
383 udi_primary_init_t pci_pri_init = {
384 .mgmt_ops = &pci_mgmt_ops,
385 .mgmt_op_flags = pci_mgmt_op_flags,
386 .mgmt_scratch_requirement = 0,
387 .enumeration_attr_list_length = 4,
388 .rdata_size = sizeof(pci_rdata_t),
389 .child_data_size = 0,
390 .per_parent_paths = 0
392 udi_ops_init_t pci_ops_list[] = {
394 PCI_OPS_BRIDGE, 1, UDI_BUS_BRIDGE_OPS_NUM,
395 sizeof(pci_child_chan_context_t),
396 (udi_ops_vector_t*)&pci_bridge_ops,
400 PCI_OPS_IRQ, 1, UDI_BUS_INTR_DISPATCH_OPS_NUM,
402 (udi_ops_vector_t*)&pci_irq_ops,
407 udi_init_t pci_init = {
408 .primary_init_info = &pci_pri_init,
409 .ops_init_list = pci_ops_list
411 const char pci_udiprops[] =
412 "properties_version 0x101\0"
413 "message 1 Acess2 Kernel\0"
415 "message 3 Acess2 PCI Bus\0"
420 "shortname acesspci\0"
421 "requires udi 0x101\0"
422 "provides udi_bridge 0x101\0"
423 "meta 1 udi_bridge\0"
424 "enumerates 4 0 100 1 bus_name string pci\0"
426 "child_bind_ops 1 0 1\0"
428 size_t pci_udiprops_size = sizeof(pci_udiprops);