3 * - By John Hodge (thePowersGang)
9 #define UDI_PCI_VERSION 0x101
11 #include <udi_physio.h>
14 #include <drv_pci.h> // acess
15 #include <udi_internal.h>
16 #include <trans_pci.h>
19 /* Copied from http://projectudi.cvs.sourceforge.net/viewvc/projectudi/udiref/driver/udi_dpt/udi_dpt.h */
20 #define DPT_SET_ATTR_BOOLEAN(attr, name, val) \
21 udi_strcpy((attr)->attr_name, (name)); \
22 (attr)->attr_type = UDI_ATTR_BOOLEAN; \
23 (attr)->attr_length = sizeof(udi_boolean_t); \
24 UDI_ATTR32_SET((attr)->attr_value, (val))
26 #define DPT_SET_ATTR32(attr, name, val) \
27 udi_strcpy((attr)->attr_name, (name)); \
28 (attr)->attr_type = UDI_ATTR_UBIT32; \
29 (attr)->attr_length = sizeof(udi_ubit32_t); \
30 UDI_ATTR32_SET((attr)->attr_value, (val))
32 #define DPT_SET_ATTR_ARRAY8(attr, name, val, len) \
33 udi_strcpy((attr)->attr_name, (name)); \
34 (attr)->attr_type = UDI_ATTR_ARRAY8; \
35 (attr)->attr_length = (len); \
36 udi_memcpy((attr)->attr_value, (val), (len))
38 #define DPT_SET_ATTR_STRING(attr, name, val, len) \
39 udi_strcpy((attr)->attr_name, (name)); \
40 (attr)->attr_type = UDI_ATTR_STRING; \
41 (attr)->attr_length = (len); \
42 udi_strncpy_rtrim((char *)(attr)->attr_value, (val), (len))
44 #define PCI_OPS_BRIDGE 1
47 #define PCI_MAX_EVENT_CBS 8
52 udi_init_context_t init_context;
59 udi_child_chan_context_t child_chan_context;
61 udi_channel_t interrupt_channel;
70 udi_pio_handle_t intr_preprocessing;
71 udi_intr_event_cb_t *event_cbs[PCI_MAX_EVENT_CBS];
72 udi_index_t event_cb_wr_ofs;
73 udi_index_t event_cb_rd_ofs;
75 } pci_child_chan_context_t;
78 void pci_usage_ind(udi_usage_cb_t *cb, udi_ubit8_t resource_level);
79 void pci_enumerate_req(udi_enumerate_cb_t *cb, udi_ubit8_t enumeration_level);
80 void pci_devmgmt_req(udi_mgmt_cb_t *cb, udi_ubit8_t mgmt_op, udi_ubit8_t parent_ID);
81 void pci_final_cleanup_req(udi_mgmt_cb_t *cb);
83 void pci_bridge_ch_event_ind(udi_channel_event_cb_t *cb);
84 void pci_unbind_req(udi_bus_bind_cb_t *cb);
85 void pci_bind_req_op(udi_bus_bind_cb_t *cb);
86 void pci_intr_attach_req(udi_intr_attach_cb_t *cb);
87 void pci_intr_attach_req__channel_spawned(udi_cb_t *gcb, udi_channel_t new_channel);
88 void pci_intr_detach_req(udi_intr_detach_cb_t *cb);
90 void pci_intr_ch_event_ind(udi_channel_event_cb_t *cb);
91 void pci_intr_event_rdy(udi_intr_event_cb_t *cb);
92 void pci_intr_event_rdy__irqs_enabled(udi_cb_t *gcb, udi_buf_t *newbuf, udi_status_t status, udi_ubit16_t result);
93 void pci_intr_handler(int irq, void *void_context);
94 void pci_intr_handle__trans_done(udi_cb_t *gcb, udi_buf_t *new_buf, udi_status_t status, udi_ubit16_t result);
96 // - Hook to physio (UDI doesn't define these)
97 int pci_pio_get_regset(udi_cb_t *gcb, udi_ubit32_t regset_idx, void **baseptr, size_t *lenptr);
100 void pci_usage_ind(udi_usage_cb_t *cb, udi_ubit8_t resource_level)
102 pci_rdata_t *rdata = UDI_GCB(cb)->context;
110 switch(resource_level)
112 case UDI_RESOURCES_CRITICAL:
113 case UDI_RESOURCES_LOW:
114 case UDI_RESOURCES_NORMAL:
115 case UDI_RESOURCES_PLENTIFUL:
119 // TODO: Initialise rdata
120 rdata->cur_iter = -1;
124 void pci_enumerate_req(udi_enumerate_cb_t *cb, udi_ubit8_t enumeration_level)
126 pci_rdata_t *rdata = UDI_GCB(cb)->context;
127 switch(enumeration_level)
129 case UDI_ENUMERATE_START:
130 case UDI_ENUMERATE_START_RESCAN:
131 rdata->cur_iter = -1;
132 case UDI_ENUMERATE_NEXT:
134 if( (rdata->cur_iter = PCI_GetDeviceByClass(0,0, rdata->cur_iter)) == -1 )
136 udi_enumerate_ack(cb, UDI_ENUMERATE_DONE, 0);
140 udi_instance_attr_list_t *attr_list = cb->attr_list;
143 PCI_GetDeviceInfo(rdata->cur_iter, &ven, &dev, &class);
145 PCI_GetDeviceVersion(rdata->cur_iter, &revision);
147 PCI_GetDeviceSubsys(rdata->cur_iter, &sven, &sdev);
149 udi_strcpy(attr_list->attr_name, "identifier");
150 attr_list->attr_length = sprintf((char*)attr_list->attr_value,
151 "%04x%04x%02x%04x%04x",
152 ven, dev, revision, sven, sdev);
154 DPT_SET_ATTR_STRING(attr_list, "bus_type", "pci", 3);
156 DPT_SET_ATTR32(attr_list, "pci_vendor_id", ven);
158 DPT_SET_ATTR32(attr_list, "pci_device_id", dev);
161 DPT_SET_ATTR32(attr_list, "pci_baseclass", class >> 16);
163 DPT_SET_ATTR32(attr_list, "pci_base_class", class >> 16); // E20010702.1
165 DPT_SET_ATTR32(attr_list, "pci_sub_class", (class >> 8) & 0xFF);
167 DPT_SET_ATTR32(attr_list, "pci_prog_if", (class >> 0) & 0xFF);
170 cb->attr_valid_length = attr_list - cb->attr_list;
171 cb->child_ID = rdata->cur_iter;
172 udi_enumerate_ack(cb, UDI_ENUMERATE_OK, 1);
177 void pci_devmgmt_req(udi_mgmt_cb_t *cb, udi_ubit8_t mgmt_op, udi_ubit8_t parent_ID)
181 void pci_final_cleanup_req(udi_mgmt_cb_t *cb)
186 void pci_bridge_ch_event_ind(udi_channel_event_cb_t *cb)
190 void pci_bind_req(udi_bus_bind_cb_t *cb)
192 // TODO: "Lock" PCI device
194 // TODO: DMA constraints
195 udi_bus_bind_ack(cb, 0, UDI_DMA_LITTLE_ENDIAN, UDI_OK);
197 void pci_unbind_req(udi_bus_bind_cb_t *cb)
201 void pci_intr_attach_req(udi_intr_attach_cb_t *cb)
203 pci_child_chan_context_t *context = UDI_GCB(cb)->context;
205 ASSERT(cb->interrupt_idx == 0);
207 context->intr_preprocessing = cb->preprocessing_handle;
208 // Check if interrupt is already bound
209 if( !UDI_HANDLE_IS_NULL(context->interrupt_channel, udi_channel_t) )
211 udi_intr_attach_ack(cb, UDI_OK);
215 udi_channel_spawn(pci_intr_attach_req__channel_spawned, UDI_GCB(cb),
216 cb->gcb.channel, cb->interrupt_idx, PCI_OPS_IRQ, context);
218 void pci_intr_attach_req__channel_spawned(udi_cb_t *gcb, udi_channel_t new_channel)
220 udi_intr_attach_cb_t *cb = UDI_MCB(gcb, udi_intr_attach_cb_t);
221 pci_child_chan_context_t *context = UDI_GCB(cb)->context;
223 if( UDI_HANDLE_IS_NULL(new_channel, udi_channel_t) )
229 context->interrupt_channel = new_channel;
231 context->interrupt_handle = IRQ_AddHandler(
232 PCI_GetIRQ(context->child_chan_context.child_ID),
233 pci_intr_handler, context);
235 udi_intr_attach_ack(cb, UDI_OK);
237 void pci_intr_detach_req(udi_intr_detach_cb_t *cb)
242 void pci_intr_ch_event_ind(udi_channel_event_cb_t *cb)
246 void pci_intr_event_rdy(udi_intr_event_cb_t *cb)
248 pci_child_chan_context_t *context = UDI_GCB(cb)->context;
250 ASSERTC(context->event_cb_rd_ofs, <, PCI_MAX_EVENT_CBS);
251 ASSERTC(context->event_cb_wr_ofs, <, PCI_MAX_EVENT_CBS);
253 LOG("Rd %i, Wr %i [WR %p{%p}]", context->event_cb_rd_ofs, context->event_cb_wr_ofs, cb, cb->event_buf);
254 if( context->event_cbs[context->event_cb_wr_ofs] )
259 context->event_cbs[context->event_cb_wr_ofs++] = cb;
260 if( context->event_cb_wr_ofs == PCI_MAX_EVENT_CBS )
261 context->event_cb_wr_ofs = 0;
263 // TODO: Fire once >= min_event_pend CBs are recieved
264 if( !context->bIntrEnabled )
266 context->bIntrEnabled = 1;
267 udi_pio_trans(pci_intr_event_rdy__irqs_enabled, NULL, context->intr_preprocessing, 0, NULL, NULL);
270 void pci_intr_event_rdy__irqs_enabled(udi_cb_t *gcb, udi_buf_t *newbuf, udi_status_t status, udi_ubit16_t result)
275 void pci_intr_handler(int irq, void *void_context)
277 pci_child_chan_context_t *context = void_context;
279 LOG("irq=%i, context=%p", irq, context);
281 if( context->event_cb_rd_ofs == context->event_cb_wr_ofs ) {
286 ASSERTC(context->event_cb_rd_ofs, <, PCI_MAX_EVENT_CBS);
287 ASSERTC(context->event_cb_wr_ofs, <, PCI_MAX_EVENT_CBS);
289 udi_intr_event_cb_t *cb = context->event_cbs[context->event_cb_rd_ofs];
290 LOG("Rd %i, Wr %i [RD %p]", context->event_cb_rd_ofs, context->event_cb_wr_ofs, cb);
291 context->event_cbs[context->event_cb_rd_ofs] = NULL;
292 context->event_cb_rd_ofs ++;
293 if( context->event_cb_rd_ofs == PCI_MAX_EVENT_CBS )
294 context->event_cb_rd_ofs = 0;
296 ASSERT(cb->gcb.scratch);
298 if( UDI_HANDLE_IS_NULL(context->intr_preprocessing, udi_pio_handle_t) )
300 // TODO: Ensure region is an interrupt region
301 udi_intr_event_ind(cb, 0);
306 *(udi_ubit8_t*)(cb->gcb.scratch) = 0;
307 // - no event info, so mem_ptr=NULL
308 udi_pio_trans(pci_intr_handle__trans_done, UDI_GCB(cb),
309 context->intr_preprocessing, 1, cb->event_buf, NULL);
314 void pci_intr_handle__trans_done(udi_cb_t *gcb, udi_buf_t *new_buf, udi_status_t status, udi_ubit16_t result)
316 udi_intr_event_cb_t *cb = UDI_MCB(gcb, udi_intr_event_cb_t);
317 LOG("cb(%p)->event_buf=%p, new_buf=%p",
318 cb, cb->event_buf, new_buf);
320 // TODO: Buffers should not change
321 cb->event_buf = new_buf;
322 cb->intr_result = result;
324 udi_ubit8_t intr_status = *(udi_ubit8_t*)(gcb->scratch);
325 if( intr_status & UDI_INTR_UNCLAIMED )
327 // Not claimed, next please.
328 // NOTE: Same as no event in the acess model
330 pci_intr_event_rdy(cb);
332 else if( intr_status & UDI_INTR_NO_EVENT )
334 // No event should be generated, return cb to pool
336 pci_intr_event_rdy(cb);
337 LOG("No event, return cb to pool");
341 LOG("Inform driver");
342 udi_intr_event_ind(cb, UDI_INTR_PREPROCESSED);
347 udi_status_t pci_pio_do_io(uint32_t child_ID, udi_ubit32_t regset_idx, udi_ubit32_t ofs, udi_ubit8_t len,
348 void *data, bool isOutput)
350 // LOG("child_ID=%i, regset_idx=%i,ofs=0x%x,len=%i,data=%p,isOutput=%b",
351 // child_ID, regset_idx, ofs, len, data, isOutput);
352 tPCIDev pciid = child_ID;
353 // TODO: Cache child mappings
357 case UDI_PCI_CONFIG_SPACE:
359 return UDI_STAT_NOT_SUPPORTED;
360 case UDI_PCI_BAR_0 ... UDI_PCI_BAR_5: {
361 Uint32 bar = PCI_GetBAR(pciid, regset_idx);
366 #define _IO(fc, type) do {\
368 /*LOG("out"#fc"(0x%x, 0x%x)",bar+ofs,*(type*)data);*/\
369 out##fc(bar+ofs, *(type*)data); \
372 *(type*)data = in##fc(bar+ofs); \
373 /*LOG("in"#fc"(0x%x) = 0x%x",bar+ofs,*(type*)data);*/\
378 case UDI_PIO_1BYTE: _IO(b, udi_ubit8_t); return UDI_OK;
379 case UDI_PIO_2BYTE: _IO(w, udi_ubit16_t); return UDI_OK;
380 case UDI_PIO_4BYTE: _IO(d, udi_ubit32_t); return UDI_OK;
381 //case UDI_PIO_8BYTE: _IO(q, uint64_t); return UDI_OK;
383 return UDI_STAT_NOT_SUPPORTED;
390 //Uint64 longbar = PCI_GetValidBAR(pciid, regset_idx, PCI_BARTYPE_MEM);
391 return UDI_STAT_NOT_SUPPORTED;
395 return UDI_STAT_NOT_UNDERSTOOD;
399 // === UDI Functions ===
400 udi_mgmt_ops_t pci_mgmt_ops = {
404 pci_final_cleanup_req
406 udi_ubit8_t pci_mgmt_op_flags[4] = {0,0,0,0};
407 udi_bus_bridge_ops_t pci_bridge_ops = {
408 pci_bridge_ch_event_ind,
414 udi_ubit8_t pci_bridge_op_flags[5] = {0,0,0,0,0};
415 udi_intr_dispatcher_ops_t pci_irq_ops = {
416 pci_intr_ch_event_ind,
419 udi_ubit8_t pci_irq_ops_flags[2] = {0,0};
420 udi_primary_init_t pci_pri_init = {
421 .mgmt_ops = &pci_mgmt_ops,
422 .mgmt_op_flags = pci_mgmt_op_flags,
423 .mgmt_scratch_requirement = 0,
424 .enumeration_attr_list_length = 7,
425 .rdata_size = sizeof(pci_rdata_t),
426 .child_data_size = 0,
427 .per_parent_paths = 0
429 udi_ops_init_t pci_ops_list[] = {
431 PCI_OPS_BRIDGE, 1, UDI_BUS_BRIDGE_OPS_NUM,
432 sizeof(pci_child_chan_context_t),
433 (udi_ops_vector_t*)&pci_bridge_ops,
437 PCI_OPS_IRQ, 1, UDI_BUS_INTR_DISPATCH_OPS_NUM,
439 (udi_ops_vector_t*)&pci_irq_ops,
444 udi_init_t pci_init = {
445 .primary_init_info = &pci_pri_init,
446 .ops_init_list = pci_ops_list
448 const char pci_udiprops[] =
449 "properties_version 0x101\0"
450 "message 1 Acess2 Kernel\0"
452 "message 3 Acess2 PCI Bus\0"
457 "shortname acesspci\0"
458 "requires udi 0x101\0"
459 "provides udi_bridge 0x101\0"
460 "meta 1 udi_bridge\0"
461 "enumerates 4 0 100 1 bus_name string pci\0"
463 "child_bind_ops 1 0 1\0"
465 size_t pci_udiprops_size = sizeof(pci_udiprops);