3 * - By John Hodge (thePowersGang)
10 #include <udi_physio.h>
13 #include <drv_pci.h> // acess
14 #include <udi_internal.h>
15 #include <trans_pci.h>
18 /* Copied from http://projectudi.cvs.sourceforge.net/viewvc/projectudi/udiref/driver/udi_dpt/udi_dpt.h */
19 #define DPT_SET_ATTR_BOOLEAN(attr, name, val) \
20 udi_strcpy((attr)->attr_name, (name)); \
21 (attr)->attr_type = UDI_ATTR_BOOLEAN; \
22 (attr)->attr_length = sizeof(udi_boolean_t); \
23 UDI_ATTR32_SET((attr)->attr_value, (val))
25 #define DPT_SET_ATTR32(attr, name, val) \
26 udi_strcpy((attr)->attr_name, (name)); \
27 (attr)->attr_type = UDI_ATTR_UBIT32; \
28 (attr)->attr_length = sizeof(udi_ubit32_t); \
29 UDI_ATTR32_SET((attr)->attr_value, (val))
31 #define DPT_SET_ATTR_ARRAY8(attr, name, val, len) \
32 udi_strcpy((attr)->attr_name, (name)); \
33 (attr)->attr_type = UDI_ATTR_ARRAY8; \
34 (attr)->attr_length = (len); \
35 udi_memcpy((attr)->attr_value, (val), (len))
37 #define DPT_SET_ATTR_STRING(attr, name, val, len) \
38 udi_strcpy((attr)->attr_name, (name)); \
39 (attr)->attr_type = UDI_ATTR_STRING; \
40 (attr)->attr_length = (len); \
41 udi_strncpy_rtrim((char *)(attr)->attr_value, (val), (len))
43 #define PCI_OPS_BRIDGE 1
46 #define PCI_MAX_EVENT_CBS 8
51 udi_init_context_t init_context;
58 udi_child_chan_context_t child_chan_context;
60 udi_channel_t interrupt_channel;
69 udi_pio_handle_t intr_preprocessing;
70 udi_intr_event_cb_t *event_cbs[PCI_MAX_EVENT_CBS];
73 } pci_child_chan_context_t;
76 void pci_usage_ind(udi_usage_cb_t *cb, udi_ubit8_t resource_level);
77 void pci_enumerate_req(udi_enumerate_cb_t *cb, udi_ubit8_t enumeration_level);
78 void pci_devmgmt_req(udi_mgmt_cb_t *cb, udi_ubit8_t mgmt_op, udi_ubit8_t parent_ID);
79 void pci_final_cleanup_req(udi_mgmt_cb_t *cb);
81 void pci_bridge_ch_event_ind(udi_channel_event_cb_t *cb);
82 void pci_unbind_req(udi_bus_bind_cb_t *cb);
83 void pci_bind_req_op(udi_bus_bind_cb_t *cb);
84 void pci_intr_attach_req(udi_intr_attach_cb_t *cb);
85 void pci_intr_attach_req__channel_spawned(udi_cb_t *gcb, udi_channel_t new_channel);
86 void pci_intr_detach_req(udi_intr_detach_cb_t *cb);
88 void pci_intr_ch_event_ind(udi_channel_event_cb_t *cb);
89 void pci_intr_event_rdy(udi_intr_event_cb_t *cb);
90 void pci_intr_handler(int irq, void *void_context);
91 void pci_intr_handle__trans_done(udi_cb_t *gcb, udi_buf_t *new_buf, udi_status_t status, udi_ubit16_t result);
93 // - Hook to physio (UDI doesn't define these)
94 int pci_pio_get_regset(udi_cb_t *gcb, udi_ubit32_t regset_idx, void **baseptr, size_t *lenptr);
97 void pci_usage_ind(udi_usage_cb_t *cb, udi_ubit8_t resource_level)
99 pci_rdata_t *rdata = UDI_GCB(cb)->context;
107 switch(resource_level)
109 case UDI_RESOURCES_CRITICAL:
110 case UDI_RESOURCES_LOW:
111 case UDI_RESOURCES_NORMAL:
112 case UDI_RESOURCES_PLENTIFUL:
116 // TODO: Initialise rdata
117 rdata->cur_iter = -1;
121 void pci_enumerate_req(udi_enumerate_cb_t *cb, udi_ubit8_t enumeration_level)
123 pci_rdata_t *rdata = UDI_GCB(cb)->context;
124 switch(enumeration_level)
126 case UDI_ENUMERATE_START:
127 case UDI_ENUMERATE_START_RESCAN:
128 rdata->cur_iter = -1;
129 case UDI_ENUMERATE_NEXT:
131 if( (rdata->cur_iter = PCI_GetDeviceByClass(0,0, rdata->cur_iter)) == -1 )
133 udi_enumerate_ack(cb, UDI_ENUMERATE_DONE, 0);
137 udi_instance_attr_list_t *attr_list = cb->attr_list;
140 PCI_GetDeviceInfo(rdata->cur_iter, &ven, &dev, &class);
142 PCI_GetDeviceVersion(rdata->cur_iter, &revision);
144 PCI_GetDeviceSubsys(rdata->cur_iter, &sven, &sdev);
146 udi_strcpy(attr_list->attr_name, "identifier");
147 attr_list->attr_length = sprintf((char*)attr_list->attr_value,
148 "%04x%04x%02x%04x%04x",
149 ven, dev, revision, sven, sdev);
151 DPT_SET_ATTR_STRING(attr_list, "bus_type", "pci", 3);
153 DPT_SET_ATTR32(attr_list, "pci_vendor_id", ven);
155 DPT_SET_ATTR32(attr_list, "pci_device_id", dev);
158 cb->attr_valid_length = attr_list - cb->attr_list;
159 cb->child_ID = rdata->cur_iter;
160 udi_enumerate_ack(cb, UDI_ENUMERATE_OK, 1);
165 void pci_devmgmt_req(udi_mgmt_cb_t *cb, udi_ubit8_t mgmt_op, udi_ubit8_t parent_ID)
169 void pci_final_cleanup_req(udi_mgmt_cb_t *cb)
174 void pci_bridge_ch_event_ind(udi_channel_event_cb_t *cb)
178 void pci_bind_req(udi_bus_bind_cb_t *cb)
180 // TODO: "Lock" PCI device
182 // TODO: DMA constraints
183 udi_bus_bind_ack(cb, 0, UDI_DMA_LITTLE_ENDIAN, UDI_OK);
185 void pci_unbind_req(udi_bus_bind_cb_t *cb)
189 void pci_intr_attach_req(udi_intr_attach_cb_t *cb)
191 pci_child_chan_context_t *context = UDI_GCB(cb)->context;
193 ASSERT(cb->interrupt_idx == 0);
195 context->intr_preprocessing = cb->preprocessing_handle;
196 // Check if interrupt is already bound
197 if( !UDI_HANDLE_IS_NULL(context->interrupt_channel, udi_channel_t) )
199 udi_intr_attach_ack(cb, UDI_OK);
203 udi_channel_spawn(pci_intr_attach_req__channel_spawned, UDI_GCB(cb),
204 cb->gcb.channel, cb->interrupt_idx, PCI_OPS_IRQ, context);
206 void pci_intr_attach_req__channel_spawned(udi_cb_t *gcb, udi_channel_t new_channel)
208 udi_intr_attach_cb_t *cb = UDI_MCB(gcb, udi_intr_attach_cb_t);
209 pci_child_chan_context_t *context = UDI_GCB(cb)->context;
211 if( UDI_HANDLE_IS_NULL(new_channel, udi_channel_t) )
217 context->interrupt_channel = new_channel;
219 context->interrupt_handle = IRQ_AddHandler(
220 PCI_GetIRQ(context->child_chan_context.child_ID),
221 pci_intr_handler, new_channel);
223 udi_intr_attach_ack(cb, UDI_OK);
225 void pci_intr_detach_req(udi_intr_detach_cb_t *cb)
230 void pci_intr_ch_event_ind(udi_channel_event_cb_t *cb)
234 void pci_intr_event_rdy(udi_intr_event_cb_t *cb)
236 pci_child_chan_context_t *context = UDI_GCB(cb)->context;
237 if( context->event_cbs[context->event_cb_wr_ofs] )
242 context->event_cbs[context->event_cb_wr_ofs++] = cb;
243 if( context->event_cb_wr_ofs == PCI_MAX_EVENT_CBS )
244 context->event_cb_wr_ofs = 0;
247 void pci_intr_handler(int irq, void *void_context)
249 pci_child_chan_context_t *context = void_context;
251 if( context->event_cb_rd_ofs == context->event_cb_wr_ofs ) {
256 udi_intr_event_cb_t *cb = context->event_cbs[context->event_cb_rd_ofs];
257 context->event_cbs[context->event_cb_rd_ofs] = NULL;
258 context->event_cb_rd_ofs ++;
259 if( context->event_cb_rd_ofs == PCI_MAX_EVENT_CBS )
260 context->event_cb_rd_ofs = 0;
262 if( UDI_HANDLE_IS_NULL(context->intr_preprocessing, udi_pio_handle_t) )
264 udi_intr_event_ind(cb, 0);
269 // - no event info, so mem_ptr=NULL
270 udi_pio_trans(pci_intr_handle__trans_done, UDI_GCB(cb),
271 context->intr_preprocessing, 1, cb->event_buf, NULL);
275 void pci_intr_handle__trans_done(udi_cb_t *gcb, udi_buf_t *new_buf, udi_status_t status, udi_ubit16_t result)
277 udi_intr_event_cb_t *cb = UDI_MCB(gcb, udi_intr_event_cb_t);
279 cb->intr_result = result;
281 udi_intr_event_ind(cb, UDI_INTR_PREPROCESSED);
285 udi_status_t pci_pio_do_io(uint32_t child_ID, udi_ubit32_t regset_idx, udi_ubit32_t ofs, udi_ubit8_t len,
286 void *data, bool isOutput)
288 // LOG("child_ID=%i, regset_idx=%i,ofs=0x%x,len=%i,data=%p,isOutput=%b",
289 // child_ID, regset_idx, ofs, len, data, isOutput);
290 tPCIDev pciid = child_ID;
291 // TODO: Cache child mappings
295 case UDI_PCI_CONFIG_SPACE:
297 return UDI_STAT_NOT_SUPPORTED;
298 case UDI_PCI_BAR_0 ... UDI_PCI_BAR_5: {
299 Uint64 bar = PCI_GetBAR(pciid, regset_idx);
304 #define _IO(fc, type) do {\
305 if( isOutput ) out##fc(bar+ofs, *(type*)data); \
306 else *(type*)data = in##fc(bar+ofs); \
310 case UDI_PIO_1BYTE: _IO(b, udi_ubit8_t); return UDI_OK;
311 case UDI_PIO_2BYTE: _IO(w, udi_ubit16_t); return UDI_OK;
312 case UDI_PIO_4BYTE: _IO(d, udi_ubit32_t); return UDI_OK;
313 //case UDI_PIO_8BYTE: _IO(q, uint64_t); return UDI_OK;
315 return UDI_STAT_NOT_SUPPORTED;
322 bar = PCI_GetValidBAR(pciid, regset_idx, PCI_BARTYPE_MEM);
323 return UDI_STAT_NOT_SUPPORTED;
327 return UDI_STAT_NOT_UNDERSTOOD;
331 // === UDI Functions ===
332 udi_mgmt_ops_t pci_mgmt_ops = {
336 pci_final_cleanup_req
338 udi_ubit8_t pci_mgmt_op_flags[4] = {0,0,0,0};
339 udi_bus_bridge_ops_t pci_bridge_ops = {
340 pci_bridge_ch_event_ind,
346 udi_ubit8_t pci_bridge_op_flags[5] = {0,0,0,0,0};
347 udi_intr_dispatcher_ops_t pci_irq_ops = {
348 pci_intr_ch_event_ind,
351 udi_ubit8_t pci_irq_ops_flags[2] = {0,0};
352 udi_primary_init_t pci_pri_init = {
353 .mgmt_ops = &pci_mgmt_ops,
354 .mgmt_op_flags = pci_mgmt_op_flags,
355 .mgmt_scratch_requirement = 0,
356 .enumeration_attr_list_length = 4,
357 .rdata_size = sizeof(pci_rdata_t),
358 .child_data_size = 0,
359 .per_parent_paths = 0
361 udi_ops_init_t pci_ops_list[] = {
363 PCI_OPS_BRIDGE, 1, UDI_BUS_BRIDGE_OPS_NUM,
364 sizeof(pci_child_chan_context_t),
365 (udi_ops_vector_t*)&pci_bridge_ops,
369 PCI_OPS_IRQ, 1, UDI_BUS_INTR_DISPATCH_OPS_NUM,
371 (udi_ops_vector_t*)&pci_irq_ops,
376 udi_init_t pci_init = {
377 .primary_init_info = &pci_pri_init,
378 .ops_init_list = pci_ops_list
380 const char pci_udiprops[] =
381 "properties_version 0x101\0"
382 "message 1 Acess2 Kernel\0"
384 "message 3 Acess2 PCI Bus\0"
389 "shortname acesspci\0"
390 "requires udi 0x101\0"
391 "provides udi_bridge 0x101\0"
392 "meta 1 udi_bridge\0"
393 "enumerates 4 0 100 1 bus_name string pci\0"
395 "child_bind_ops 1 0 1\0"
397 size_t pci_udiprops_size = sizeof(pci_udiprops);