2 #ifndef _PCNETFAST3__HW_H_
3 #define _PCNETFAST3__HW_H_
5 typedef struct sInitBlock32 tInitBlock32;
6 typedef struct sTxDesc_3 tTxDesc_3;
7 typedef struct sRxDesc_3 tRxDesc_3;
11 Uint32 Mode; // [0:15]: MODE, [20:23] RLen, [28:31] TLen
12 Uint32 PhysAddr0; // MAC Address
13 Uint32 PhysAddr1; // [0:15] MAC Addres
14 Uint32 LAdrF0; // Logical Address Filter (CRC on multicast MAC, top 6 bits index bitmap)
16 Uint32 RDRA; // Rx Descriptor Ring Address
17 Uint32 TDRA; // Tx Descriptor Ring Address
20 // SWSTYLE=3: 32-bit allowing burst mode
21 #define RXDESC_FLG_OWN (1<<31)
22 #define RXDESC_FLG_ENP (1<<24)
23 #define RXDESC_FLG_STP (1<<25)
26 Uint32 Count; // [0:11] Message Byte Count
27 Uint32 Flags; // [0:11] BCNT, [23] BPE, ENP, STP, BUFF, CRC, OFLO, FRAM, ERR, OWN
32 #define TXDESC_FLG1_OWN (1 << 31)
33 #define TXDESC_FLG1_ADDFCS (1<<29)
34 #define TXDESC_FLG1_STP (1 << 25)
35 #define TXDESC_FLG1_ENP (1 << 24)
38 Uint32 Flags0; // Status mostly
39 Uint32 Flags1; // [0:11] BCNT
50 REG_RDP = 0x10, // 16 bit
51 REG_RAP = 0x14, // 8-bit
52 REG_RESET = 0x18, // 16-bit
53 REG_BDP = 0x1C, // 16-bit
56 #define CSR_STATUS_INIT (1<< 0)
57 #define CSR_STATUS_STRT (1<< 1)
58 #define CSR_STATUS_IENA (1<< 6)
59 #define CSR_STATUS_INTR (1<< 7)
60 #define CSR_STATUS_IDON (1<< 8)
61 #define CSR_STATUS_TINT (1<< 9)
62 #define CSR_STATUS_RINT (1<<10)
66 CSR_STATUS, // CSR0 - Am79C973/Am79C975 Controller Status
67 CSR_IBA0, // CSR1 - Initialization Block Address[15:0]
68 CSR_IBA1, // CSR2 - Initialization Block Address[31:16]
69 CSR_INTMASK, // CSR3 - Interrupt Masks and Deferral Control
71 CSR_LAF0 = 8, // CSR8 - Logical Address Filter[15:0]
72 CSR_LAF1 = 9, // CSR9 - Logical Address Filter[31:16]
73 CSR_LAF2 = 10, // CSR10 - Logical Address Filter[47:32]
74 CSR_LAF3 = 11, // CSR11 - Logical Address Filter[63:48]
75 CSR_MAC0 = 12, // CSR12 - Physical Address[15:0]
76 CSR_MAC1 = 13, // CSR13 - Physical Address[31:16]
77 CSR_MAC2 = 14, // CSR14 - Physical Address[47:32]
78 CSR_MODE = 15, // CSR15 - Mode
80 CSR_RXBASE0 = 24, // CSR24 - Base Address of Receive Ring Lower
81 CSR_RXBASE1 = 25, // CSR25 - Base Address of Receive Ring Upper
82 CSR_TXBASE0 = 30, // CSR26 - Base Address of Transmit Ring Lower
83 CSR_TXBASE1 = 31, // CSR27 - Base Address of Transmit Ring Upper
85 CSR_RXLENGTH = 76, // CSR76 - Receive Ring Length
86 CSR_TXLENGTH = 78, // CSR78 - Transmit Ring Length
92 BCR_PHYCS = 32, // BCR32 - Internal PHY Control and Status
93 BCR_PHYADDR, // BCR33 - Internal PHY Address
94 BCR_PHYMGMT, // BCR34 - Internal PHY Management Data