2 * Acess2 VIA Rhine II Driver (VT6102)
3 * - By John Hodge (thePowersGang)
5 #ifndef _VIARHINEII__RHINE2_HW_H_
6 #define _VIARHINEII__RHINE2_HW_H_
25 REG_CUR_TX_DESC = 0x1C,
27 REG_GFTEST = 0x54, REG_RFTCMD,
28 REG_TFTCMD, REG_GFSTATUS,
29 REG_BNRY, _REG_BNRY_HI,
35 #define RCR_SEP (1 << 0) // Accept error packets
36 #define RCR_AR (1 << 1) // Accept small packets (< 64 bytes)
37 #define RCR_AM (1 << 2) // Accept multicast packets
38 #define RCR_AB (1 << 3) // Accept broadcast packets
39 #define RCR_PROM (1 << 4) // Accept any addressed packet
40 #define RCR_RRFT(v) (((v)&7)<<5) // Recieve FIFO threshold (64,32,128,256,512,768,1024,s&f)
42 #define TCR_RSVD0 (1 << 0) // reserved
43 #define TCR_LB(v) (((v)&3)<<1) // Loopback mode (normal, internal, MII, 223/other)
44 #define TCR_OFSET (1 << 3) // Backoff algo (VIA, Standard)
45 #define TCR_RSVD1 (1 << 4) // reserved
46 #define TCR_TRSF(v) (((v)&7)<<5) // Transmit FIFO threshold
53 Uint16 Length; // 11 bits, Bit 15 is owner bit
54 Uint16 BufferSize; // 11 bits, Bit 15 is chain bit (means the packet continues in the next desc)
57 Uint32 RDBranchAddress; // ? - I'm guessing it's the next descriptor in the chain
60 #define RSR_RERR (1 << 0) // Receiver error
61 #define RSR_CRC (1 << 1) // CRC Error
62 #define RSR_FAE (1 << 2) // Frame Alignment error
63 #define RSR_FOV (1 << 3) // FIFO Overflow
64 #define RSR_LONG (1 << 4) // Long packet
65 #define RSR_RUNT (1 << 5) // Runt packet
66 #define RSR_SERR (1 << 6) // System Error
67 #define RSR_BUFF (1 << 7) // Buffer underflow
68 #define RSR_EDP (1 << 8) // End of Packet
69 #define RSR_STP (1 << 9) // Start of Packet
70 #define RSR_CHN (1 << 10) // Chain buffer
71 #define RSR_PHY (1 << 11) // Physical address match
72 #define RSR_BAR (1 << 12) // Broadcast packet
73 #define RSR_MAR (1 << 13) // Multicast packet
74 #define RSR_RESVD (1 << 14) // reserved
75 #define RSR_RXOK (1 << 15) // Recieved OK
80 Uint16 BufferSize; // 11 bits, bit 15 is chain
84 Uint32 TDBranchAddress; // Bit 0: Disable interrupt