2 * Acess2 VIA Rhine II Driver (VT6102)
3 * - By John Hodge (thePowersGang)
5 #ifndef _VIARHINEII__RHINE2_HW_H_
6 #define _VIARHINEII__RHINE2_HW_H_
25 REG_CUR_TX_DESC = 0x1C,
27 REG_GFTEST = 0x54, REG_RFTCMD,
28 REG_TFTCMD, REG_GFSTATUS,
29 REG_BNRY, _REG_BNRY_HI,
35 #define RCR_SEP (1 << 0) // Accept error packets
36 #define RCR_AR (1 << 1) // Accept small packets (< 64 bytes)
37 #define RCR_AM (1 << 2) // Accept multicast packets
38 #define RCR_AB (1 << 3) // Accept broadcast packets
39 #define RCR_PROM (1 << 4) // Accept any addressed packet
40 #define RCR_RRFT(v) (((v)&7)<<5) // Recieve FIFO threshold (64,32,128,256,512,768,1024,s&f)
42 #define TCR_RSVD0 (1 << 0) // reserved
43 #define TCR_LB(v) (((v)&3)<<1) // Loopback mode (normal, internal, MII, 223/other)
44 #define TCR_OFSET (1 << 3) // Backoff algo (VIA, Standard)
45 #define TCR_RSVD1 (1 << 4) // reserved
46 #define TCR_TRSF(v) (((v)&7)<<5) // Transmit FIFO threshold
48 #define CR0_INIT (1 << 0)
49 #define CR0_STRT (1 << 1)
50 #define CR0_STOP (1 << 2)
51 #define CR0_RXON (1 << 3)
52 #define CR0_TXON (1 << 4)
53 #define CR0_TDMD (1 << 5)
54 #define CR0_RDMD (1 << 6)
55 #define CR0_RESV (1 << 7) // reserved
57 #define CR1_EREN (1 << 0) // Early recieve enable
58 #define CR1_RESV0 (1 << 1)
59 #define CR1_FDX (1 << 2) // Full/Half-duplex selector
60 #define CR1_DPOLL (1 << 3) // Disable automatic polling
61 #define CR1_RESV1 (1 << 4)
62 #define CR1_TDMD (1 << 5)
63 #define CR1_RDMD (1 << 6)
64 #define CR1_SFRST (1 << 7) // Software reset
66 #define ISR0_PRX (1 << 0) // Packet recieved
67 #define ISR0_PTX (1 << 1) // Packet transmitted successfully
68 #define ISR0_RXE (1 << 2) // RX Error
69 #define ISR0_TXE (1 << 3) // TX Error
70 #define ISR0_TU (1 << 4) // Transmit buffer underflow
71 #define ISR0_RU (1 << 5) // Recieve buffer link error
72 #define ISR0_BE (1 << 6) // PCI Bus error
73 #define ISR0_CNT (1 << 7) // CRC error / missed packet counter overflow
75 #define ISR1_ERI (1 << 0) // Early recieve interrupt
76 #define ISR1_UDFI (1 << 1) // TX FIFO underflow event
77 #define ISR1_OVFI (1 << 2) // Recieve overflow
78 #define ISR1_PKTR (1 << 3) // FIFO overflow (?"next packet race with current packet")
79 #define ISR1_NORBF (1 << 4) // No more recieve buffers avaiable (overflow essentialy)
80 #define ISR1_ABTI (1 << 5) // Transmission abort due to excessive collisions
81 #define ISR1_SRCI (1 << 6) // Port state change
82 #define ISR1_GENI (1 << 7) // General purpose interrupt
89 Uint16 Length; // 11 bits, Bit 15 is owner bit
90 Uint16 BufferSize; // 11 bits, Bit 15 is chain bit (means the packet continues in the next desc)
93 Uint32 RDBranchAddress; // ? - I'm guessing it's the next descriptor in the chain
96 #define RSR_RERR (1 << 0) // Receiver error
97 #define RSR_CRC (1 << 1) // CRC Error
98 #define RSR_FAE (1 << 2) // Frame Alignment error
99 #define RSR_FOV (1 << 3) // FIFO Overflow
100 #define RSR_LONG (1 << 4) // Long packet
101 #define RSR_RUNT (1 << 5) // Runt packet
102 #define RSR_SERR (1 << 6) // System Error
103 #define RSR_BUFF (1 << 7) // Buffer underflow
104 #define RSR_EDP (1 << 8) // End of Packet
105 #define RSR_STP (1 << 9) // Start of Packet
106 #define RSR_CHN (1 << 10) // Chain buffer
107 #define RSR_PHY (1 << 11) // Physical address match
108 #define RSR_BAR (1 << 12) // Broadcast packet
109 #define RSR_MAR (1 << 13) // Multicast packet
110 #define RSR_RESVD (1 << 14) // reserved
111 #define RSR_RXOK (1 << 15) // Recieved OK
116 Uint16 BufferSize; // 11 bits, bit 15 is chain
119 Uint32 TXBufferStart;
120 Uint32 TDBranchAddress; // Bit 0: Disable interrupt
123 #define TD_TCR_CRC (1 << 0) // Disable CRC generation
124 #define TD_TCR_STP (1 << 5) // First descriptor in packet
125 #define TD_TCR_EDP (1 << 6) // Last descriptor in packet
126 #define TD_TCR_IC (1 << 7) // Interrupt when transmitted
128 #define TD_TSR_OWN (1 << 31)