2 * Acess2 Kernel - AHCI Driver
3 * - By John Hodge (thePowersGang)
6 * - Hardware Definitions
8 #ifndef _AHCI__AHCI_HW_H_
9 #define _AHCI__AHCI_HW_H_
11 #define AHCI_CAP_S64A (1 << 31) // Supports 64-bit addressing
12 #define AHCI_CAP_SNCQ (1 << 30) // Supports Native Command Queuing
13 #define AHCI_CAP_SXS (1 << 5) // Support External SATA
14 #define AHCI_CAP_NCS (31 << 8) // Number of command slots (mask)
16 #define AHCI_GHC_AE (1 << 31) // AHCI Enable
17 #define AHCI_GHC_MRSM (1 << 2) // MSI Revert to Single Message
18 #define AHCI_GHC_IE (1 << 1) // Interrupt Enable
19 #define ACHI_GHC_HR (1 << 0) // HBA Reset (Clears once complete)
21 #define AHCI_PxIS_CPDS (1 << 31) // Cold Port Detect Status
22 #define AHCI_PxIS_TFES (1 << 30) // Task File Error Status
23 #define AHCI_PxIS_HBFS (1 << 29) // Host Bus Fatal error Status
24 #define AHCI_PxIS_HBDS (1 << 28) // Host Bus Data error Status
25 #define AHCI_PxIS_IFS (1 << 27) // Interface Fatal error Status
26 #define AHCI_PxIS_INFS (1 << 26) // Interface Non-Fatal error status
27 #define AHCI_PxIS_OFS (1 << 24) // OverFlow Status
28 #define AHCI_PxIS_IPMS (1 << 23) // Incorrect Port Multipier Status
29 #define AHCI_PxIS_PRCS (1 << 22) // PhyRdy Change Status
30 #define AHCI_PxIS_DMPS (1 << 7) // Device Mechanical Presence Status
31 #define AHCI_PxIS_PCS (1 << 6) // Port Connect change Status
32 #define AHCI_PxIS_DPS (1 << 5) // Descriptor Processed
33 #define AHCI_PxIS_UFI (1 << 4) // Unknown FIX Interrupt
34 #define AHCI_PxIS_SDBS (1 << 3) // Set Device Bits Interrupt
35 #define AHCI_PxIS_DSS (1 << 2) // DMA Setup FIS Interrupt
36 #define AHCI_PxIS_PSS (1 << 1) // PIO Setup FIX Interrupt
37 #define AHCI_PxIS_DHRS (1 << 0) // Device to Host Register FIS Interrupt
39 #define AHCI_PxCMD_ICC (15 << 28) // Interface Communication Control (mask)
40 #define AHCI_PxCMD_ASP (1 << 27) // Agressive Slumber / Partial
41 #define AHCI_PxCMD_ALPE (1 << 26) // Agressive Link Power Management Enable
42 #define AHCI_PxCMD_DLAE (1 << 25) // Drive LED on ATAPI Enable
43 #define AHCI_PxCMD_ATAPI (1 << 24) // Device is ATAPI
44 #define AHCI_PxCMD_APSTE (1 << 23) // Automatic Partial to Slumber Transitions Enabled
45 #define AHCI_PxCMD_FBSCP (1 << 22) // FIS-based Switching Capable Port
46 #define AHCI_PxCMD_ESP (1 << 21) // External SATA Port
47 #define AHCI_PxCMD_CPD (1 << 20) // Cold Presence Detection
48 #define AHCI_PxCMD_MPSP (1 << 19) // Mechanical Presence Switch attached to Port
49 #define AHCI_PxCMD_HPCP (1 << 18) // Hot Plut Capable Port
50 #define AHCI_PxCMD_PMA (1 << 17) // Port Multiplier Attached
51 #define AHCI_PxCMD_CPS (1 << 16) // Cold Presence State
52 #define AHCI_PxCMD_CR (1 << 15) // Command List Running
53 #define AHCI_PxCMD_FR (1 << 14) // FIS Receive Running
54 #define AHCI_PxCMD_MPSS (1 << 13) // Mechanical Presence Switch State
55 #define AHCI_PxCMD_CCS (31 << 8) // Current Command Slot (mask)
56 #define AHCI_PxCMD_FRE (1 << 4) // FIS Receive Enable
57 #define AHCI_PxCMD_CLO (1 << 3) // Command List Override
58 #define AHCI_PxCMD_POD (1 << 2) // Power On Device
59 #define AHCI_PxCMD_SUD (1 << 1) // Spin-Up Device
60 #define AHCI_PxCMD_ST (1 << 0) // Start
64 Uint32 CAP; // Host Capabilities
65 Uint32 GHC; // Global Host Control;
66 Uint32 IS; // Interrupt Status
67 Uint32 PI; // Ports Implemented
69 Uint32 CCC_CTL; // Command Completion Coalsecing Control
70 Uint32 CCC_PORTS; // Command Completion Coalsecing Ports
71 Uint32 EM_LOC; // Enclosure Management Location
72 Uint32 EM_CTL; // Enclosure management control
73 Uint32 CAP2; // Host Capabilities Extended
74 Uint32 BOHC; // BIOS/OS Handoff Control and Status
76 Uint16 _padding[(0x100-0x2C)/2];
80 Uint32 PxCLB; // Command List Base Address
81 Uint32 PxCLBU; // (High of above)
82 Uint32 PxFB; // FIS Base Address
83 Uint32 PxFBU; // (high of above)
84 Uint32 PxIS; // Interrupt Status
85 Uint32 PxIE; // Interrupt Enable
86 Uint32 PxCMD; // Command and Status
88 Uint32 PxTFD; // Task File Data
89 Uint32 PxSIG; // Signature
90 Uint32 PxSSTS; // Serial ATA Status
91 Uint32 PxSCTL; // Serial ATA Control
92 Uint32 PxSERR; // Serial ATA Error
93 Uint32 PxSACT; // Serial ATA Active
94 Uint32 PxCI; // Command Issue
95 Uint32 PxSNTF; // Serial ATA Notification
96 Uint32 PxFBS; // FIS-based Switching Control
97 Uint32 _resvd2[(0x70-0x44)/4];
107 Uint32 CTBA; // 128-byte alignment
114 Uint32 DBA; // Data base address
115 Uint32 DBAU; // (upper)
117 Uint32 DBC; // Data byte count (31: IOC, 21:0 count) 0=1, 1=2, ...