2 * Acess2 Kernel - AHCI Driver
3 * - By John Hodge (thePowersGang)
6 * - Hardware Definitions
8 #ifndef _AHCI__AHCI_HW_H_
9 #define _AHCI__AHCI_HW_H_
11 #define AHCI_CAP_S64A (1 << 31) // Supports 64-bit addressing
12 #define AHCI_CAP_SNCQ (1 << 30) // Supports Native Command Queuing
13 #define AHCI_CAP_SXS (1 << 5) // Support External SATA
15 #define AHCI_GHC_AE (1 << 31) // AHCI Enable
16 #define AHCI_GHC_MRSM (1 << 2) // MSI Revert to Single Message
17 #define AHCI_GHC_IE (1 << 1) // Interrupt Enable
18 #define ACHI_GHC_HR (1 << 0) // HBA Reset (Clears once complete)
22 Uint32 CAP; // Host Capabilities
23 Uint32 GHC; // Global Host Control;
24 Uint32 IS; // Interrupt Status
25 Uint32 PI; // Ports Implemented
27 Uint32 CCC_CTL; // Command Completion Coalsecing Control
28 Uint32 CCC_PORTS; // Command Completion Coalsecing Ports
29 Uint32 EM_LOC; // Enclosure Management Location
30 Uint32 EM_CTL; // Enclosure management control
31 Uint32 CAP2; // Host Capabilities Extended
32 Uint32 BOHC; // BIOS/OS Handoff Control and Status
34 Uint16 _padding[(0x100-0x2C)/2];
38 Uint32 PxCLB; // Command List Base Address
39 Uint32 PxCLBU; // (High of above)
40 Uint32 PxFB; // FIS Base Address
41 Uint32 PxFBU; // (high of above)
42 Uint32 PxIS; // Interrupt Status
43 Uint32 PxIE; // Interrupt Enable
44 Uint32 PxCMD; // Command and Status
46 Uint32 PxTFD; // Task File Data
47 Uint32 PxSIG; // Signature
48 Uint32 PxSSTS; // Serial ATA Status
49 Uint32 PxSCTL; // Serial ATA Control
50 Uint32 PxSERR; // Serial ATA Error
51 Uint32 PxSACT; // Serial ATA Active
52 Uint32 PxCI; // Command Issue
53 Uint32 PxSNTF; // Serial ATA Notification
54 Uint32 PxFBS; // FIS-based Switching Control
55 Uint32 _resvd2[(0x70-0x44)/4];
65 Uint32 CTBA; // 128-byte alignment
72 Uint32 DBA; // Data base address
73 Uint32 DBAU; // (upper)
75 Uint32 DBC; // Data byte count (31: IOC, 21:0 count) 0=1, 1=2, ...