2 * Acess2 IDE Harddisk Driver
5 * Disk Input/Output control
9 #include <modules.h> // Needed for error codes
16 #define IO_DELAY() do{inb(0x80); inb(0x80); inb(0x80); inb(0x80);}while(0)
19 #define IDE_PRI_BASE 0x1F0
20 #define IDE_PRI_CTRL 0x3F6
21 #define IDE_SEC_BASE 0x170
22 #define IDE_SEC_CTRL 0x376
24 #define IDE_PRDT_LAST 0x8000
27 \brief Commands to be sent to HDD_CMD
47 Uint32 PBufAddr; // Physical Buffer Address
48 Uint16 Bytes; // Size of transfer entry
49 Uint16 Flags; // Flags
50 } __attribute__ ((packed)) tPRDT_Ent;
53 * \brief Structure returned by the ATA IDENTIFY command
58 Uint16 Usused1[9]; // 10
59 char SerialNum[20]; // 20
60 Uint16 Usused2[3]; // 23
61 char FirmwareVer[8]; // 27
62 char ModelNumber[40]; // 47
63 Uint16 SectPerInt; // 48 - Low byte only
65 Uint16 Capabilities[2]; // 51
66 Uint16 Unused4[2]; // 53
67 Uint16 ValidExtData; // 54
68 Uint16 Unused5[5]; // 59
69 Uint16 SizeOfRWMultiple; // 60
70 Uint32 Sectors28; // LBA 28 Sector Count
71 Uint16 Unused6[100-62];
72 Uint64 Sectors48; // LBA 48 Sector Count
73 Uint16 Unused7[256-104];
74 } __attribute__ ((packed)) tIdentify;
77 int ATA_SetupIO(void);
78 Uint64 ATA_GetDiskSize(int Disk);
79 Uint16 ATA_GetBasePort(int Disk);
81 int ATA_ReadDMA(Uint8 Disk, Uint64 Address, Uint Count, void *Buffer);
82 int ATA_WriteDMA(Uint8 Disk, Uint64 Address, Uint Count, const void *Buffer);
84 void ATA_IRQHandlerPri(int UNUSED(IRQ), void *UNUSED(Ptr));
85 void ATA_IRQHandlerSec(int UNUSED(IRQ), void *UNUSED(Ptr));
87 Uint8 ATA_int_BusMasterReadByte(int Ofs);
88 Uint32 ATA_int_BusMasterReadDWord(int Ofs);
89 void ATA_int_BusMasterWriteByte(int Ofs, Uint8 Value);
90 void ATA_int_BusMasterWriteDWord(int Ofs, Uint32 Value);
93 // - BusMaster IO Addresses
94 Uint32 gATA_BusMasterBase; //!< True Address (IO/MMIO)
95 Uint8 *gATA_BusMasterBasePtr; //!< Paging Mapped MMIO (If needed)
99 volatile int gaATA_IRQs[2] = {0};
100 tThread *gATA_WaitingThreads[2];
101 // - Locks to avoid tripping
102 tMutex glaATA_ControllerLock[2];
104 void *gATA_Buffers[2];
106 tPRDT_Ent gATA_PRDTs[2] = {
107 {0, 512, IDE_PRDT_LAST},
108 {0, 512, IDE_PRDT_LAST}
110 tPAddr gaATA_PRDT_PAddrs[2];
114 * \brief Sets up the ATA controller's DMA mode
116 int ATA_SetupIO(void)
122 // Get IDE Controller's PCI Entry
123 ent = PCI_GetDeviceByClass(0x010100, 0xFFFF00, -1);
124 LOG("ent = %i", ent);
125 gATA_BusMasterBase = PCI_GetBAR(ent, 4);
126 if( gATA_BusMasterBase == 0 ) {
127 Log_Warning("ATA", "It seems that there is no Bus Master Controller on this machine. Get one");
128 // TODO: Use PIO mode instead
129 LEAVE('i', MODULE_ERR_NOTNEEDED);
130 return MODULE_ERR_NOTNEEDED;
133 LOG("BAR5 = 0x%x", PCI_GetBAR(ent, 5));
134 LOG("IRQ = %i", PCI_GetIRQ(ent));
137 if( !(gATA_BusMasterBase & 1) )
139 if( gATA_BusMasterBase < 0x100000 )
140 gATA_BusMasterBasePtr = (void*)(KERNEL_BASE | (tVAddr)gATA_BusMasterBase);
142 gATA_BusMasterBasePtr = (void*)( MM_MapHWPages( gATA_BusMasterBase, 1 ) + (gATA_BusMasterBase&0xFFF) );
143 LOG("gATA_BusMasterBasePtr = %p", gATA_BusMasterBasePtr);
146 // Bit 0 is left set as a flag to other functions
147 LOG("gATA_BusMasterBase = IO 0x%x", gATA_BusMasterBase & ~1);
150 // Register IRQs and get Buffers
151 IRQ_AddHandler( gATA_IRQPri, ATA_IRQHandlerPri, NULL );
152 IRQ_AddHandler( gATA_IRQSec, ATA_IRQHandlerSec, NULL );
155 gATA_Buffers[0] = (void*)MM_AllocDMA(1, 32, &paddr);
156 gATA_PRDTs[0].PBufAddr = paddr;
157 gATA_Buffers[1] = (void*)MM_AllocDMA(1, 32, &paddr);
158 gATA_PRDTs[1].PBufAddr = paddr;
160 LOG("gATA_PRDTs = {PBufAddr: 0x%x, PBufAddr: 0x%x}", gATA_PRDTs[0].PBufAddr, gATA_PRDTs[1].PBufAddr);
162 // TODO: Ensure that this is within 32-bits
163 gaATA_PRDT_PAddrs[0] = MM_GetPhysAddr( &gATA_PRDTs[0] );
164 gaATA_PRDT_PAddrs[1] = MM_GetPhysAddr( &gATA_PRDTs[1] );
165 LOG("gaATA_PRDT_PAddrs = {0x%P, 0x%P}", gaATA_PRDT_PAddrs[0], gaATA_PRDT_PAddrs[1]);
167 if( gaATA_PRDT_PAddrs[0] >> 32 || gaATA_PRDT_PAddrs[1] >> 32 ) {
168 Log_Error("ATA", "Physical addresses of PRDTs are not in 32-bits (%P and %P)",
169 gaATA_PRDT_PAddrs[0], gaATA_PRDT_PAddrs[1]);
170 LEAVE('i', MODULE_ERR_MISC);
171 return MODULE_ERR_MISC;
174 ATA_int_BusMasterWriteDWord(4, gaATA_PRDT_PAddrs[0]);
175 ATA_int_BusMasterWriteDWord(12, gaATA_PRDT_PAddrs[1]);
177 // Enable controllers
178 outb(IDE_PRI_BASE+1, 1);
179 outb(IDE_SEC_BASE+1, 1);
180 outb(IDE_PRI_CTRL, 0);
181 outb(IDE_SEC_CTRL, 0);
183 // Make sure interrupts are ACKed
184 ATA_int_BusMasterWriteByte(2, 0x4);
185 ATA_int_BusMasterWriteByte(10, 0x4);
188 LEAVE('i', MODULE_ERR_OK);
189 return MODULE_ERR_OK;
193 * \brief Get the size (in sectors) of a disk
194 * \param Disk Disk to get size of
195 * \return Number of sectors reported
197 * Does an ATA IDENTIFY
199 Uint64 ATA_GetDiskSize(int Disk)
208 ENTER("iDisk", Disk);
210 base = ATA_GetBasePort( Disk );
212 // Send Disk Selector
213 if(Disk & 1) // Slave
219 // Check for a floating bus
220 if( 0xFF == inb(base+7) ) {
226 // Check for the controller
227 // - Write to two RW ports and attempt to read back
228 outb(base+0x02, 0x66);
229 outb(base+0x03, 0xFF);
230 if(inb(base+0x02) != 0x66 || inb(base+0x03) != 0xFF) {
231 LOG("No controller");
237 outb(base+7, HDD_IDENTIFY);
239 val = inb(base+7); // Read status
240 LOG("val = 0x%02x", val);
243 return 0; // Disk does not exist
246 // Poll until BSY clears or ERR is set
248 while( (val & 0x80) && !(val & 1) )
250 LOG("BSY unset (0x%x)", val);
251 // and, wait for DRQ to set
252 while( !(val & 0x08) && !(val & 1))
254 LOG("DRQ set (0x%x)", val);
256 // Check for an error
259 return 0; // Error occured, so return false
263 for( i = 0; i < 256; i++ )
264 data.buf[i] = inw(base);
266 // Return the disk size
267 if(data.identify.Sectors48 != 0) {
268 LEAVE('X', data.identify.Sectors48);
269 return data.identify.Sectors48;
272 LEAVE('x', data.identify.Sectors28);
273 return data.identify.Sectors28;
278 * \fn Uint16 ATA_GetPortBase(int Disk)
279 * \brief Returns the base port for a given disk
281 Uint16 ATA_GetBasePort(int Disk)
285 case 0: case 1: return IDE_PRI_BASE;
286 case 2: case 3: return IDE_SEC_BASE;
291 int ATA_DoDMA(Uint8 Disk, Uint64 Address, Uint Count, int bWrite, void *Buffer)
293 int cont = (Disk>>1)&1; // Controller ID
296 int bUseBounceBuffer;
298 ENTER("iDisk XAddress iCount bbWrite pBuffer", Disk, Address, Count, bWrite, Buffer);
300 // Check if the count is small enough
301 if(Count > MAX_DMA_SECTORS) {
302 Log_Warning("ATA", "Passed too many sectors for a bulk DMA (%i > %i)",
303 Count, MAX_DMA_SECTORS);
308 // Hack to make debug hexdump noticable
310 memset(Buffer, 0xFF, Count*SECTOR_SIZE);
313 // Get exclusive access to the disk controller
314 Mutex_Acquire( &glaATA_ControllerLock[ cont ] );
317 gATA_PRDTs[ cont ].Bytes = Count * SECTOR_SIZE;
319 // Detemine if the transfer can be done directly
320 tPAddr buf_ps = MM_GetPhysAddr(Buffer);
321 tPAddr buf_pe = MM_GetPhysAddr((char*)Buffer + Count * SECTOR_SIZE - 1);
322 if( buf_pe == buf_ps + Count * SECTOR_SIZE - 1 ) {
326 // Over 32-bits, need to copy anyway
327 bUseBounceBuffer = 1;
328 LOG("%P over 32-bit, using bounce buffer", buf_pe);
333 // TODO: Handle splitting the read into two?
334 bUseBounceBuffer = 1;
335 LOG("%P + 0x%x != %P, using bounce buffer", buf_ps, Count * SECTOR_SIZE, buf_pe);
338 // Set up destination / source buffers
339 if( bUseBounceBuffer ) {
340 gATA_PRDTs[cont].PBufAddr = MM_GetPhysAddr(gATA_Buffers[cont]);
342 memcpy(gATA_Buffers[cont], Buffer, Count * SECTOR_SIZE);
345 gATA_PRDTs[cont].PBufAddr = MM_GetPhysAddr(Buffer);
349 base = ATA_GetBasePort(Disk);
352 gaATA_IRQs[cont] = 0;
355 // TODO: What the ____ does this do?
358 outb(IDE_PRI_CTRL, 4);
360 outb(IDE_PRI_CTRL, 0);
363 outb(IDE_SEC_CTRL, 4);
365 outb(IDE_SEC_CTRL, 0);
370 if( Address > 0x0FFFFFFF ) // Use LBA48
372 outb(base+0x6, 0x40 | (disk << 4));
374 outb(base+0x2, 0 >> 8); // Upper Sector Count
375 outb(base+0x3, Address >> 24); // Low 2 Addr
376 outb(base+0x4, Address >> 28); // Mid 2 Addr
377 outb(base+0x5, Address >> 32); // High 2 Addr
381 // Magic, Disk, High Address nibble
382 outb(base+0x06, 0xE0 | (disk << 4) | ((Address >> 24) & 0x0F));
383 //outb(base+0x06, 0xA0 | (disk << 4) | ((Address >> 24) & 0x0F));
387 //outb(base+0x01, 0x01); //?
388 outb(base+0x02, Count & 0xFF); // Sector Count
389 outb(base+0x03, Address & 0xFF); // Low Addr
390 outb(base+0x04, (Address >> 8) & 0xFF); // Middle Addr
391 outb(base+0x05, (Address >> 16) & 0xFF); // High Addr
393 LOG("Starting Transfer");
395 // HACK: Ensure the PRDT is reset
396 ATA_int_BusMasterWriteDWord(cont*8+4, gaATA_PRDT_PAddrs[cont]);
397 ATA_int_BusMasterWriteByte(cont*8, 4); // Reset IRQ
399 LOG("gATA_PRDTs[%i].Bytes = %i", cont, gATA_PRDTs[cont].Bytes);
400 if( Address > 0x0FFFFFFF )
401 outb(base+0x07, bWrite ? HDD_DMA_W48 : HDD_DMA_R48); // Command (LBA48)
403 outb(base+0x07, bWrite ? HDD_DMA_W28 : HDD_DMA_R28); // Command (LBA28)
405 // Intialise timeout timer
406 Threads_ClearEvent(THREAD_EVENT_SHORTWAIT|THREAD_EVENT_TIMER);
407 tTimer *timeout = Time_AllocateTimer(NULL, NULL);
408 Time_ScheduleTimer(timeout, ATA_TIMEOUT);
409 gATA_WaitingThreads[cont] = Proc_GetCurThread();
412 ATA_int_BusMasterWriteByte( cont * 8, (bWrite ? 0 : 8) | 1 ); // Write(0)/Read(8) and start
414 // Wait for transfer to complete
415 Uint32 ev = Threads_WaitEvents(THREAD_EVENT_SHORTWAIT|THREAD_EVENT_TIMER);
416 Time_FreeTimer(timeout);
418 if( ev & THREAD_EVENT_TIMER ) {
419 Log_Notice("ATA", "Timeout of %i ms exceeded", ATA_TIMEOUT);
423 ATA_int_BusMasterWriteByte( cont * 8, (bWrite ? 0 : 8) ); // Write/Read and stop
427 Uint8 val = inb(base+0x7);
428 LOG("Status byte = 0x%02x, Controller Status = 0x%02x",
429 val, ATA_int_BusMasterReadByte(cont * 8 + 2));
435 if( gaATA_IRQs[cont] == 0 )
437 if( ATA_int_BusMasterReadByte(cont * 8 + 2) & 0x4 ) {
438 Log_Error("ATA", "BM Status reports an interrupt, but none recieved");
439 ATA_int_BusMasterWriteByte(cont*8 + 2, 4); // Clear interrupt
444 Debug_HexDump("ATA", Buffer, 512);
447 // Release controller lock
448 Mutex_Release( &glaATA_ControllerLock[ cont ] );
450 "Timeout on disk %i (%s sector 0x%llx)",
451 Disk, bWrite ? "Writing" : "Reading", Address);
457 LOG("Transfer Completed & Acknowledged");
459 // Copy to destination buffer (if bounce was used and it was a read)
460 if( bUseBounceBuffer && !bWrite )
461 memcpy( Buffer, gATA_Buffers[cont], Count*SECTOR_SIZE );
462 // Release controller lock
463 Mutex_Release( &glaATA_ControllerLock[ cont ] );
470 * \fn int ATA_ReadDMA(Uint8 Disk, Uint64 Address, Uint Count, void *Buffer)
471 * \return Boolean Failure
473 int ATA_ReadDMA(Uint8 Disk, Uint64 Address, Uint Count, void *Buffer)
475 return ATA_DoDMA(Disk, Address, Count, 0, Buffer);
480 * \fn int ATA_WriteDMA(Uint8 Disk, Uint64 Address, Uint Count, void *Buffer)
481 * \brief Write up to \a MAX_DMA_SECTORS to a disk
482 * \param Disk Disk ID to write to
483 * \param Address LBA of first sector
484 * \param Count Number of sectors to write (must be >= \a MAX_DMA_SECTORS)
485 * \param Buffer Source buffer for data
486 * \return Boolean Failure
488 int ATA_WriteDMA(Uint8 Disk, Uint64 Address, Uint Count, const void *Buffer)
490 return ATA_DoDMA(Disk, Address, Count, 1, (void*)Buffer);
494 * \brief Primary ATA Channel IRQ handler
496 void ATA_IRQHandlerPri(int UNUSED(IRQ), void *UNUSED(Ptr))
500 // IRQ bit set for Primary Controller
501 val = ATA_int_BusMasterReadByte( 0x2 );
502 LOG("IRQ val = 0x%x", val);
505 LOG("IRQ hit (val = 0x%x)", val);
506 ATA_int_BusMasterWriteByte( 0x2, 4 );
508 Threads_PostEvent(gATA_WaitingThreads[0], THREAD_EVENT_SHORTWAIT);
514 * \brief Second ATA Channel IRQ handler
516 void ATA_IRQHandlerSec(int UNUSED(IRQ), void *UNUSED(Ptr))
519 // IRQ bit set for Secondary Controller
520 val = ATA_int_BusMasterReadByte( 0xA );
521 LOG("IRQ val = 0x%x", val);
523 LOG("IRQ hit (val = 0x%x)", val);
524 ATA_int_BusMasterWriteByte( 0xA, 4 );
526 Threads_PostEvent(gATA_WaitingThreads[1], THREAD_EVENT_SHORTWAIT);
532 * \brief Read an 8-bit value from a Bus Master register
533 * \param Ofs Register offset
535 Uint8 ATA_int_BusMasterReadByte(int Ofs)
537 if( gATA_BusMasterBase & 1 )
538 return inb( (gATA_BusMasterBase & ~1) + Ofs );
540 return *(Uint8*)(gATA_BusMasterBasePtr + Ofs);
544 * \brief Read an 32-bit value from a Bus Master register
545 * \param Ofs Register offset
547 Uint32 ATA_int_BusMasterReadDWord(int Ofs)
549 if( gATA_BusMasterBase & 1 )
550 return ind( (gATA_BusMasterBase & ~1) + Ofs );
552 return *(Uint32*)(gATA_BusMasterBasePtr + Ofs);
556 * \brief Writes a byte to a Bus Master Register
557 * \param Ofs Register Offset
558 * \param Value Value to write
560 void ATA_int_BusMasterWriteByte(int Ofs, Uint8 Value)
562 if( gATA_BusMasterBase & 1 )
563 outb( (gATA_BusMasterBase & ~1) + Ofs, Value );
565 *(Uint8*)(gATA_BusMasterBasePtr + Ofs) = Value;
569 * \brief Writes a 32-bit value to a Bus Master Register
570 * \param Ofs Register offset
571 * \param Value Value to write
573 void ATA_int_BusMasterWriteDWord(int Ofs, Uint32 Value)
575 if( gATA_BusMasterBase & 1 )
576 outd( (gATA_BusMasterBase & ~1) + Ofs, Value );
578 *(Uint32*)(gATA_BusMasterBasePtr + Ofs) = Value;