2 * Acess2 IDE Harddisk Driver
5 * Disk Input/Output control
9 #include <modules.h> // Needed for error codes
16 #define IO_DELAY() do{inb(0x80); inb(0x80); inb(0x80); inb(0x80);}while(0)
19 #define IDE_PRI_BASE 0x1F0
20 #define IDE_PRI_CTRL 0x3F6
21 #define IDE_SEC_BASE 0x170
22 #define IDE_SEC_CTRL 0x376
24 #define IDE_PRDT_LAST 0x8000
27 \brief Commands to be sent to HDD_CMD
47 Uint32 PBufAddr; // Physical Buffer Address
48 Uint16 Bytes; // Size of transfer entry
49 Uint16 Flags; // Flags
50 } __attribute__ ((packed)) tPRDT_Ent;
53 * \brief Structure returned by the ATA IDENTIFY command
58 Uint16 Usused1[9]; // 10
59 char SerialNum[20]; // 20
60 Uint16 Usused2[3]; // 23
61 char FirmwareVer[8]; // 27
62 char ModelNumber[40]; // 47
63 Uint16 SectPerInt; // 48 - Low byte only
65 Uint16 Capabilities[2]; // 51
66 Uint16 Unused4[2]; // 53
67 Uint16 ValidExtData; // 54
68 Uint16 Unused5[5]; // 59
69 Uint16 SizeOfRWMultiple; // 60
70 Uint32 Sectors28; // LBA 28 Sector Count
71 Uint16 Unused6[100-62];
72 Uint64 Sectors48; // LBA 48 Sector Count
73 Uint16 Unused7[256-104];
74 } __attribute__ ((packed)) tIdentify;
77 int ATA_SetupIO(void);
78 Uint64 ATA_GetDiskSize(int Disk);
79 Uint16 ATA_GetBasePort(int Disk);
81 int ATA_ReadDMA(Uint8 Disk, Uint64 Address, Uint Count, void *Buffer);
82 int ATA_WriteDMA(Uint8 Disk, Uint64 Address, Uint Count, const void *Buffer);
84 void ATA_IRQHandlerPri(int UNUSED(IRQ), void *UNUSED(Ptr));
85 void ATA_IRQHandlerSec(int UNUSED(IRQ), void *UNUSED(Ptr));
87 Uint8 ATA_int_BusMasterReadByte(int Ofs);
88 Uint32 ATA_int_BusMasterReadDWord(int Ofs);
89 void ATA_int_BusMasterWriteByte(int Ofs, Uint8 Value);
90 void ATA_int_BusMasterWriteDWord(int Ofs, Uint32 Value);
93 // - BusMaster IO Addresses
94 Uint32 gATA_BusMasterBase; //!< True Address (IO/MMIO)
95 Uint8 *gATA_BusMasterBasePtr; //!< Paging Mapped MMIO (If needed)
99 volatile int gaATA_IRQs[2] = {0};
100 tThread *gATA_WaitingThreads[2];
101 // - Locks to avoid tripping
102 tMutex glaATA_ControllerLock[2];
104 void *gATA_Buffers[2];
106 tPRDT_Ent gATA_PRDTs[2] = {
107 {0, 512, IDE_PRDT_LAST},
108 {0, 512, IDE_PRDT_LAST}
110 tPAddr gaATA_PRDT_PAddrs[2];
114 * \brief Sets up the ATA controller's DMA mode
116 int ATA_SetupIO(void)
122 // Get IDE Controller's PCI Entry
123 ent = PCI_GetDeviceByClass(0x010100, 0xFFFF00, -1);
124 LOG("ent = %i", ent);
125 gATA_BusMasterBase = PCI_GetBAR(ent, 4);
126 if( gATA_BusMasterBase == 0 ) {
127 Log_Warning("ATA", "Unable to find a Bus Master DMA controller");
128 // TODO: Use PIO mode instead
129 LEAVE('i', MODULE_ERR_NOTNEEDED);
130 return MODULE_ERR_NOTNEEDED;
133 LOG("BAR5 = 0x%x", PCI_GetBAR(ent, 5));
134 LOG("IRQ = %i", PCI_GetIRQ(ent));
137 if( gATA_BusMasterBase & 1 )
139 gATA_BusMasterBase &= ~1;
140 LOG("gATA_BusMasterBase = IO 0x%x", gATA_BusMasterBase);
145 gATA_BusMasterBasePtr = MM_MapHWPages( gATA_BusMasterBase, 1 ) + (gATA_BusMasterBase&0xFFF);
146 LOG("gATA_BusMasterBasePtr = %p", gATA_BusMasterBasePtr);
149 // Register IRQs and get Buffers
150 IRQ_AddHandler( gATA_IRQPri, ATA_IRQHandlerPri, NULL );
151 IRQ_AddHandler( gATA_IRQSec, ATA_IRQHandlerSec, NULL );
154 gATA_Buffers[0] = (void*)MM_AllocDMA(1, 32, &paddr);
155 gATA_PRDTs[0].PBufAddr = paddr;
156 gATA_Buffers[1] = (void*)MM_AllocDMA(1, 32, &paddr);
157 gATA_PRDTs[1].PBufAddr = paddr;
159 LOG("gATA_PRDTs = {PBufAddr: 0x%x, PBufAddr: 0x%x}", gATA_PRDTs[0].PBufAddr, gATA_PRDTs[1].PBufAddr);
161 // TODO: Ensure that this is within 32-bits
162 gaATA_PRDT_PAddrs[0] = MM_GetPhysAddr( &gATA_PRDTs[0] );
163 gaATA_PRDT_PAddrs[1] = MM_GetPhysAddr( &gATA_PRDTs[1] );
164 LOG("gaATA_PRDT_PAddrs = {0x%P, 0x%P}", gaATA_PRDT_PAddrs[0], gaATA_PRDT_PAddrs[1]);
166 if( gaATA_PRDT_PAddrs[0] >> 32 || gaATA_PRDT_PAddrs[1] >> 32 ) {
167 Log_Error("ATA", "Physical addresses of PRDTs are not in 32-bits (%P and %P)",
168 gaATA_PRDT_PAddrs[0], gaATA_PRDT_PAddrs[1]);
169 LEAVE('i', MODULE_ERR_MISC);
170 return MODULE_ERR_MISC;
173 ATA_int_BusMasterWriteDWord(4, gaATA_PRDT_PAddrs[0]);
174 ATA_int_BusMasterWriteDWord(12, gaATA_PRDT_PAddrs[1]);
176 // Enable controllers
177 outb(IDE_PRI_BASE+1, 1);
178 outb(IDE_SEC_BASE+1, 1);
179 outb(IDE_PRI_CTRL, 0);
180 outb(IDE_SEC_CTRL, 0);
182 // Make sure interrupts are ACKed
183 ATA_int_BusMasterWriteByte(2, 0x4);
184 ATA_int_BusMasterWriteByte(10, 0x4);
187 LEAVE('i', MODULE_ERR_OK);
188 return MODULE_ERR_OK;
192 * \brief Get the size (in sectors) of a disk
193 * \param Disk Disk to get size of
194 * \return Number of sectors reported
196 * Does an ATA IDENTIFY
198 Uint64 ATA_GetDiskSize(int Disk)
207 ENTER("iDisk", Disk);
209 base = ATA_GetBasePort( Disk );
211 // Send Disk Selector
212 if(Disk & 1) // Slave
218 // Check for a floating bus
219 if( 0xFF == inb(base+7) ) {
225 // Check for the controller
226 // - Write to two RW ports and attempt to read back
227 outb(base+0x02, 0x66);
228 outb(base+0x03, 0xFF);
229 if(inb(base+0x02) != 0x66 || inb(base+0x03) != 0xFF) {
230 LOG("No controller");
236 outb(base+7, HDD_IDENTIFY);
238 val = inb(base+7); // Read status
239 LOG("val = 0x%02x", val);
242 return 0; // Disk does not exist
245 // Poll until BSY clears or ERR is set
247 while( (val & 0x80) && !(val & 1) )
249 LOG("BSY unset (0x%x)", val);
250 // and, wait for DRQ to set
251 while( !(val & 0x08) && !(val & 1))
253 LOG("DRQ set (0x%x)", val);
255 // Check for an error
258 return 0; // Error occured, so return false
262 for( i = 0; i < 256; i++ )
263 data.buf[i] = inw(base);
265 // Return the disk size
266 if(data.identify.Sectors48 != 0) {
267 LEAVE('X', data.identify.Sectors48);
268 return data.identify.Sectors48;
271 LEAVE('x', data.identify.Sectors28);
272 return data.identify.Sectors28;
277 * \fn Uint16 ATA_GetPortBase(int Disk)
278 * \brief Returns the base port for a given disk
280 Uint16 ATA_GetBasePort(int Disk)
284 case 0: case 1: return IDE_PRI_BASE;
285 case 2: case 3: return IDE_SEC_BASE;
290 int ATA_DoDMA(Uint8 Disk, Uint64 Address, Uint Count, int bWrite, void *Buffer)
292 int cont = (Disk>>1)&1; // Controller ID
295 int bUseBounceBuffer;
297 ENTER("iDisk XAddress iCount bbWrite pBuffer", Disk, Address, Count, bWrite, Buffer);
299 // Check if the count is small enough
300 if(Count > MAX_DMA_SECTORS) {
301 Log_Warning("ATA", "Passed too many sectors for a bulk DMA (%i > %i)",
302 Count, MAX_DMA_SECTORS);
307 // Hack to make debug hexdump noticable
309 memset(Buffer, 0xFF, Count*SECTOR_SIZE);
312 // Get exclusive access to the disk controller
313 Mutex_Acquire( &glaATA_ControllerLock[ cont ] );
316 gATA_PRDTs[ cont ].Bytes = Count * SECTOR_SIZE;
318 // Detemine if the transfer can be done directly
319 tPAddr buf_ps = MM_GetPhysAddr(Buffer);
320 tPAddr buf_pe = MM_GetPhysAddr((char*)Buffer + Count * SECTOR_SIZE - 1);
321 if( buf_pe == buf_ps + Count * SECTOR_SIZE - 1 ) {
325 // Over 32-bits, need to copy anyway
326 bUseBounceBuffer = 1;
327 LOG("%P over 32-bit, using bounce buffer", buf_pe);
332 // TODO: Handle splitting the read into two?
333 bUseBounceBuffer = 1;
334 LOG("%P + 0x%x != %P, using bounce buffer", buf_ps, Count * SECTOR_SIZE, buf_pe);
337 // Set up destination / source buffers
338 if( bUseBounceBuffer ) {
339 gATA_PRDTs[cont].PBufAddr = MM_GetPhysAddr(gATA_Buffers[cont]);
341 memcpy(gATA_Buffers[cont], Buffer, Count * SECTOR_SIZE);
344 gATA_PRDTs[cont].PBufAddr = MM_GetPhysAddr(Buffer);
348 base = ATA_GetBasePort(Disk);
351 gaATA_IRQs[cont] = 0;
354 // TODO: What the ____ does this do?
357 outb(IDE_PRI_CTRL, 4);
359 outb(IDE_PRI_CTRL, 0);
362 outb(IDE_SEC_CTRL, 4);
364 outb(IDE_SEC_CTRL, 0);
369 if( Address > 0x0FFFFFFF ) // Use LBA48
371 outb(base+0x6, 0x40 | (disk << 4));
373 outb(base+0x2, 0 >> 8); // Upper Sector Count
374 outb(base+0x3, Address >> 24); // Low 2 Addr
375 outb(base+0x4, Address >> 28); // Mid 2 Addr
376 outb(base+0x5, Address >> 32); // High 2 Addr
380 // Magic, Disk, High Address nibble
381 outb(base+0x06, 0xE0 | (disk << 4) | ((Address >> 24) & 0x0F));
382 //outb(base+0x06, 0xA0 | (disk << 4) | ((Address >> 24) & 0x0F));
386 //outb(base+0x01, 0x01); //?
387 outb(base+0x02, Count & 0xFF); // Sector Count
388 outb(base+0x03, Address & 0xFF); // Low Addr
389 outb(base+0x04, (Address >> 8) & 0xFF); // Middle Addr
390 outb(base+0x05, (Address >> 16) & 0xFF); // High Addr
392 LOG("Starting Transfer");
394 // HACK: Ensure the PRDT is reset
395 ATA_int_BusMasterWriteDWord(cont*8+4, gaATA_PRDT_PAddrs[cont]);
396 ATA_int_BusMasterWriteByte(cont*8, 4); // Reset IRQ
398 LOG("gATA_PRDTs[%i].Bytes = %i", cont, gATA_PRDTs[cont].Bytes);
399 if( Address > 0x0FFFFFFF )
400 outb(base+0x07, bWrite ? HDD_DMA_W48 : HDD_DMA_R48); // Command (LBA48)
402 outb(base+0x07, bWrite ? HDD_DMA_W28 : HDD_DMA_R28); // Command (LBA28)
404 // Intialise timeout timer
405 Threads_ClearEvent(THREAD_EVENT_SHORTWAIT|THREAD_EVENT_TIMER);
406 tTimer *timeout = Time_AllocateTimer(NULL, NULL);
407 Time_ScheduleTimer(timeout, ATA_TIMEOUT);
408 gATA_WaitingThreads[cont] = Proc_GetCurThread();
411 ATA_int_BusMasterWriteByte( cont * 8, (bWrite ? 0 : 8) | 1 ); // Write(0)/Read(8) and start
413 // Wait for transfer to complete
414 Uint32 ev = Threads_WaitEvents(THREAD_EVENT_SHORTWAIT|THREAD_EVENT_TIMER);
415 Time_FreeTimer(timeout);
417 if( ev & THREAD_EVENT_TIMER ) {
418 Log_Notice("ATA", "Timeout of %i ms exceeded", ATA_TIMEOUT);
422 ATA_int_BusMasterWriteByte( cont * 8, (bWrite ? 0 : 8) ); // Write/Read and stop
426 Uint8 val = inb(base+0x7);
427 LOG("Status byte = 0x%02x, Controller Status = 0x%02x",
428 val, ATA_int_BusMasterReadByte(cont * 8 + 2));
434 if( gaATA_IRQs[cont] == 0 )
436 if( ATA_int_BusMasterReadByte(cont * 8 + 2) & 0x4 ) {
437 Log_Error("ATA", "BM Status reports an interrupt, but none recieved");
438 ATA_int_BusMasterWriteByte(cont*8 + 2, 4); // Clear interrupt
443 Debug_HexDump("ATA", Buffer, 512);
446 // Release controller lock
447 Mutex_Release( &glaATA_ControllerLock[ cont ] );
449 "Timeout on disk %i (%s sector 0x%llx)",
450 Disk, bWrite ? "Writing" : "Reading", Address);
456 LOG("Transfer Completed & Acknowledged");
458 // Copy to destination buffer (if bounce was used and it was a read)
459 if( bUseBounceBuffer && !bWrite )
460 memcpy( Buffer, gATA_Buffers[cont], Count*SECTOR_SIZE );
461 // Release controller lock
462 Mutex_Release( &glaATA_ControllerLock[ cont ] );
469 * \fn int ATA_ReadDMA(Uint8 Disk, Uint64 Address, Uint Count, void *Buffer)
470 * \return Boolean Failure
472 int ATA_ReadDMA(Uint8 Disk, Uint64 Address, Uint Count, void *Buffer)
474 return ATA_DoDMA(Disk, Address, Count, 0, Buffer);
479 * \fn int ATA_WriteDMA(Uint8 Disk, Uint64 Address, Uint Count, void *Buffer)
480 * \brief Write up to \a MAX_DMA_SECTORS to a disk
481 * \param Disk Disk ID to write to
482 * \param Address LBA of first sector
483 * \param Count Number of sectors to write (must be >= \a MAX_DMA_SECTORS)
484 * \param Buffer Source buffer for data
485 * \return Boolean Failure
487 int ATA_WriteDMA(Uint8 Disk, Uint64 Address, Uint Count, const void *Buffer)
489 return ATA_DoDMA(Disk, Address, Count, 1, (void*)Buffer);
493 * \brief Primary ATA Channel IRQ handler
495 void ATA_IRQHandlerPri(int UNUSED(IRQ), void *UNUSED(Ptr))
499 // IRQ bit set for Primary Controller
500 val = ATA_int_BusMasterReadByte( 0x2 );
501 LOG("IRQ val = 0x%x", val);
504 LOG("IRQ hit (val = 0x%x)", val);
505 ATA_int_BusMasterWriteByte( 0x2, 4 );
507 Threads_PostEvent(gATA_WaitingThreads[0], THREAD_EVENT_SHORTWAIT);
513 * \brief Second ATA Channel IRQ handler
515 void ATA_IRQHandlerSec(int UNUSED(IRQ), void *UNUSED(Ptr))
518 // IRQ bit set for Secondary Controller
519 val = ATA_int_BusMasterReadByte( 0xA );
520 LOG("IRQ val = 0x%x", val);
522 LOG("IRQ hit (val = 0x%x)", val);
523 ATA_int_BusMasterWriteByte( 0xA, 4 );
525 Threads_PostEvent(gATA_WaitingThreads[1], THREAD_EVENT_SHORTWAIT);
531 * \brief Read an 8-bit value from a Bus Master register
532 * \param Ofs Register offset
534 Uint8 ATA_int_BusMasterReadByte(int Ofs)
536 if( gATA_BusMasterBasePtr )
537 return *(Uint8*)(gATA_BusMasterBasePtr + Ofs);
539 return inb( gATA_BusMasterBase + Ofs );
543 * \brief Read an 32-bit value from a Bus Master register
544 * \param Ofs Register offset
546 Uint32 ATA_int_BusMasterReadDWord(int Ofs)
548 if( gATA_BusMasterBasePtr )
549 return *(Uint32*)(gATA_BusMasterBasePtr + Ofs);
551 return ind( gATA_BusMasterBase + Ofs );
555 * \brief Writes a byte to a Bus Master Register
556 * \param Ofs Register Offset
557 * \param Value Value to write
559 void ATA_int_BusMasterWriteByte(int Ofs, Uint8 Value)
561 if( gATA_BusMasterBasePtr )
562 *(Uint8*)(gATA_BusMasterBasePtr + Ofs) = Value;
564 outb( gATA_BusMasterBase + Ofs, Value );
568 * \brief Writes a 32-bit value to a Bus Master Register
569 * \param Ofs Register offset
570 * \param Value Value to write
572 void ATA_int_BusMasterWriteDWord(int Ofs, Uint32 Value)
574 if( gATA_BusMasterBasePtr )
575 *(Uint32*)(gATA_BusMasterBasePtr + Ofs) = Value;
577 outd( gATA_BusMasterBase + Ofs, Value );