3 * - By John Hodge (thePowersGang)
13 #define PERIODIC_SIZE 1024
15 typedef struct sEHCI_CapRegs tEHCI_CapRegs;
16 typedef struct sEHCI_OpRegs tEHCI_OpRegs;
17 typedef struct sEHCI_iTD tEHCI_iTD;
18 typedef struct sEHCI_siTD tEHCI_siTD;
19 typedef struct sEHCI_qTD tEHCI_qTD;
20 typedef struct sEHCI_QH tEHCI_QH;
21 typedef struct sEHCI_Controller tEHCI_Controller;
25 Uint8 CapLength; // Byte offset of Operational registers
27 Uint16 HCIVersion; // BCD Version
29 * Structural Parameters
31 * 0: 3 = Number of ports on this controller
32 * 4 = Port Power Control
33 * 5: 6 = Reserved (ZERO)
34 * 7 = Port Routing Rules
35 * 8:11 = Number of ports per companion controller
36 * 12:15 = Number of companion controllers
37 * 16 = Port Indicators
38 * 17:19 = Reserved (ZERO)
39 * 20:23 = Debug Port Number
40 * 24:31 = Reserved (ZERO)
44 * Capability Parameters
46 * 0 = 64-bit Addressing Capability
47 * 1 = Programmable Frame List Flag
48 * 2 = Asyncronous Schedule Park Capability
50 * 4: 7 = Isochronous Scheduling Threshold
51 * 8:15 = EHCI Extended Capabilitys Pointer (0 = None)
52 * 16:31 = Reserved (ZERO)
56 * Companion Port Route Description
64 * USB Command Register
66 * 0 = Run/Stop (Stop, Run)
67 * 1 = Host Controller Reset
68 * 2: 3 = Frame List Size (1024 entries, 512, 256, Reserved)
69 * 4 = Periodic Schedule Enable
70 * 5 = Asynchronous Schedule Enable
71 * 6 = Interrupt on Async Advance Doorbell
72 * 7 = Light Host Controller Reset
73 * 8: 9 = Asynchronous Schedule Park Mode Count
74 * 10 = Reserved (ZERO)
75 * 11 = Asynchronous Schedule Park Mode Enable
76 * 12:15 = Reserved (ZERO)
77 * 16:23 = Interrupt Threshold Control
78 * 31:24 = Reserved (ZERO)
85 * 1 = USB Error Interrupt
86 * 2 = Port Change Detect
87 * 3 = Frame List Rollover
88 * 4 = Host System Error
89 * 5 = Interrupt on Async Advance
90 * 6:11 = Reserved (ZERO)
93 * 14 = Periodic Schedule Status
94 * 15 = Asynchronous Schedule Status
95 * 16:31 = Reserved ?(Zero)
97 volatile Uint32 USBSts;
99 * USB Interrupt Enable Register
101 * 0 = USB Interrupt Enable
102 * 1 = USB Error Interrupt Enable
103 * 2 = Port Change Interrupt Enable
104 * 3 = Frame List Rollover Enable
105 * 4 = Host System Error Enable
106 * 5 = Interrupt on Async Advance Enable
107 * 6:31 = Reserved (Zero)
111 * Current microframe number (14 bits)
113 * Bits 14:3 are used as n index into PeridocListBase
115 volatile Uint32 FrIndex;
117 * Control Data Structure Segment Register
119 * Most significant 32-bits of all addresses (only used if "64-bit addressing capability" is set)
121 Uint32 CtrlDSSegment;
123 * Periodic Frame List Base Address Register
125 Uint32 PeridocListBase;
127 * Current Asynchronous List Address Register
129 Uint32 AsyncListAddr;
131 Uint32 _resvd[(0x40-0x1C)/4];
133 * Configure Flag Register
135 * - When 0, all ports are routed to a USB1.1 controller
137 * 0 = Configure Flag - Driver sets when controller is configured
138 * 1:31 = Reserved (ZERO)
142 * Port Status and Control Register
144 * 0 = Current Connect Status
145 * 1 = Connect Status Change
147 * 3 = Port Enable Change
148 * 4 = Over-current Active
149 * 5 = Over-current change
150 * 6 = Force Port Resume
153 * 9 = Reserved (ZERO)
154 * 10:11 = Line Status (Use to detect non USB2) [USB2, USB2, USB1.1, USB2]
156 * 13 = Port Owner (Set to 1 to give to companion controller)
157 * 14:15 = Port Indicator Control (Off, Amber, Green, Undef)
158 * 16:19 = Port Test Control
159 * 20 = Wake on Connect Enable
160 * 21 = Wake on Disconnect Enable
161 * 22 = Wake on Over-current Enable
162 * 23:31 = Reserved (ZERO)
164 volatile Uint32 PortSC[15];
167 #define USBCMD_Run 0x0001
168 #define USBCMD_HCReset 0x0002
169 #define USBCMD_PeriodicEnable 0x0010
170 #define USBCMD_AsyncEnable 0x0020
172 #define USBINTR_IOC 0x0001
173 #define USBINTR_Error 0x0002
174 #define USBINTR_PortChange 0x0004
175 #define USBINTR_FrameRollover 0x0008
176 #define USBINTR_HostSystemError 0x0010
177 #define USBINTR_AsyncAdvance 0x0020
179 #define PORTSC_CurrentConnectStatus 0x0001
180 #define PORTSC_ConnectStatusChange 0x0002
181 #define PORTSC_PortEnabled 0x0004
182 #define PORTSC_PortEnableChange 0x0008
183 #define PORTSC_OvercurrentActive 0x0010
184 #define PORTSC_OvercurrentChange 0x0020
185 #define PORTSC_ForcePortResume 0x0040
186 #define PORTSC_Suspend 0x0080
187 #define PORTSC_PortReset 0x0100
188 #define PORTSC_Reserved1 0x0200
189 #define PORTSC_LineStatus_MASK 0x0C00
190 #define PORTSC_LineStatus_SE0 0x0000
191 #define PORTSC_LineStatus_Jstate 0x0400
192 #define PORTSC_LineStatus_Kstate 0x0800
193 #define PORTSC_LineStatus_Undef 0x0C00
194 #define PORTSC_PortPower 0x1000
195 #define PORTSC_PortOwner 0x2000
196 #define PORTSC_PortIndicator_MASK 0xC000
197 #define PORTSC_PortIndicator_Off 0x0000
198 #define PORTSC_PortIndicator_Amber 0x4000
199 #define PORTSC_PortIndicator_Green 0x800
201 // Isochronous (High-Speed) Transfer Descriptor
214 // 0:10 - Max packet size
216 Uint32 BufferPointers[8]; // Page aligned, low 12 bits are overloaded
219 // Split Transaction Isochronous Transfer Descriptor
231 // Queue Element Transfer Descriptor
235 Uint32 Link2; // Used when there's a short packet
237 Uint32 Pages[5]; //First has offset in low 12 bits
239 // Internals (32 bytes = 4x 64-bit pointers)
240 tUSBHostCb *Callback;
243 } __attribute__((aligned(32)));
249 Uint32 HLink; // Horizontal link
259 } __attribute__((aligned(32)));
266 struct sEHCI_Controller
269 tThread *InterruptThread;
273 tEHCI_CapRegs *CapRegs;
274 tEHCI_OpRegs *OpRegs;
276 int InterruptLoad[PERIODIC_SIZE];
277 tEHCI_QH *LastAsyncHead;
279 tMutex PeriodicListLock;
280 Uint32 *PeriodicQueue;
281 tEHCI_QH *PeriodicQueueV[PERIODIC_SIZE];
283 tEHCI_QH *QHPools[(256*16)*sizeof(tEHCI_QH)/PAGE_SIZE]; // [PAGE_SIZE/64]
284 tEHCI_qTD *TDPool[PAGE_SIZE/sizeof(tEHCI_qTD)];