3 * - By John Hodge (thePowersGang)
11 #define PERIODIC_SIZE 1024
13 typedef struct sEHCI_CapRegs tEHCI_CapRegs;
14 typedef struct sEHCI_OpRegs tEHCI_OpRegs;
15 typedef struct sEHCI_iTD tEHCI_iTD;
16 typedef struct sEHCI_siTD tEHCI_siTD;
17 typedef struct sEHCI_qTD tEHCI_qTD;
18 typedef struct sEHCI_QH tEHCI_QH;
19 typedef struct sEHCI_Controller tEHCI_Controller;
23 Uint8 CapLength; // Byte offset of Operational registers
25 Uint16 HCIVersion; // BCD Version
27 * Structural Parameters
29 * 0: 3 = Number of ports on this controller
30 * 4 = Port Power Control
31 * 5: 6 = Reserved (ZERO)
32 * 7 = Port Routing Rules
33 * 8:11 = Number of ports per companion controller
34 * 12:15 = Number of companion controllers
35 * 16 = Port Indicators
36 * 17:19 = Reserved (ZERO)
37 * 20:23 = Debug Port Number
38 * 24:31 = Reserved (ZERO)
42 * Capability Parameters
44 * 0 = 64-bit Addressing Capability
45 * 1 = Programmable Frame List Flag
46 * 2 = Asyncronous Schedule Park Capability
48 * 4: 7 = Isochronous Scheduling Threshold
49 * 8:15 = EHCI Extended Capabilitys Pointer (0 = None)
50 * 16:31 = Reserved (ZERO)
54 * Companion Port Route Description
62 * USB Command Register
64 * 0 = Run/Stop (Stop, Run)
65 * 1 = Host Controller Reset
66 * 2: 3 = Frame List Size (1024 entries, 512, 256, Reserved)
67 * 4 = Periodic Schedule Enable
68 * 5 = Asynchronous Schedule Enable
69 * 6 = Interrupt on Async Advance Doorbell
70 * 7 = Light Host Controller Reset
71 * 8: 9 = Asynchronous Schedule Park Mode Count
72 * 10 = Reserved (ZERO)
73 * 11 = Asynchronous Schedule Park Mode Enable
74 * 12:15 = Reserved (ZERO)
75 * 16:23 = Interrupt Threshold Control
76 * 31:24 = Reserved (ZERO)
83 * 1 = USB Error Interrupt
84 * 2 = Port Change Detect
85 * 3 = Frame List Rollover
86 * 4 = Host System Error
87 * 5 = Interrupt on Async Advance
88 * 6:11 = Reserved (ZERO)
91 * 14 = Periodic Schedule Status
92 * 15 = Asynchronous Schedule Status
93 * 16:31 = Reserved ?(Zero)
97 * USB Interrupt Enable Register
99 * 0 = USB Interrupt Enable
100 * 1 = USB Error Interrupt Enable
101 * 2 = Port Change Interrupt Enable
102 * 3 = Frame List Rollover Enable
103 * 4 = Host System Error Enable
104 * 5 = Interrupt on Async Advance Enable
105 * 6:31 = Reserved (Zero)
109 * Current microframe number (14 bits)
111 * Bits 14:3 are used as n index into PeridocListBase
115 * Control Data Structure Segment Register
117 * Most significant 32-bits of all addresses (only used if "64-bit addressing capability" is set)
119 Uint32 CtrlDSSegment;
121 * Periodic Frame List Base Address Register
123 Uint32 PeridocListBase;
125 * Current Asynchronous List Address Register
127 Uint32 AsyncListAddr;
129 Uint32 _resvd[(0x40-0x1C)/4];
131 * Configure Flag Register
133 * - When 0, all ports are routed to a USB1.1 controller
135 * 0 = Configure Flag - Driver sets when controller is configured
136 * 1:31 = Reserved (ZERO)
140 * Port Status and Control Register
142 * 0 = Current Connect Status
143 * 1 = Connect Status Change
145 * 3 = Port Enable Change
146 * 4 = Over-current Active
147 * 5 = Over-current change
148 * 6 = Force Port Resume
151 * 9 = Reserved (ZERO)
152 * 10:11 = Line Status (Use to detect non USB2) [USB2, USB2, USB1.1, USB2]
154 * 13 = Port Owner (Set to 1 to give to companion controller)
155 * 14:15 = Port Indicator Control (Off, Amber, Green, Undef)
156 * 16:19 = Port Test Control
157 * 20 = Wake on Connect Enable
158 * 21 = Wake on Disconnect Enable
159 * 22 = Wake on Over-current Enable
160 * 23:31 = Reserved (ZERO)
165 #define USBCMD_Run 0x0001
166 #define USBCMD_HCReset 0x0002
167 #define USBCMD_PeriodicEnable 0x0010
168 #define USBCMD_AsyncEnable 0x0020
170 #define USBINTR_IOC 0x0001
171 #define USBINTR_Error 0x0002
172 #define USBINTR_PortChange 0x0004
173 #define USBINTR_FrameRollover 0x0008
174 #define USBINTR_HostSystemError 0x0010
175 #define USBINTR_AsyncAdvance 0x0020
177 // Isochronous (High-Speed) Transfer Descriptor
190 // 0:10 - Max packet size
192 Uint32 BufferPointers[8]; // Page aligned, low 12 bits are overloaded
195 // Split Transaction Isochronous Transfer Descriptor
207 // Queue Element Transfer Descriptor
211 Uint32 Link2; // Used when there's a short packet
213 Uint32 Pages[5]; //First has offset in low 12 bits
215 // Internals (32 bytes = 4x 64-bit pointers)
216 tUSBHostCb *Callback;
219 } __attribute__((aligned(32)));
225 Uint32 HLink; // Horizontal link
235 } __attribute__((aligned(32)));
242 struct sEHCI_Controller
245 tEHCI_CapRegs *CapRegs;
246 tEHCI_OpRegs *OpRegs;
248 int InterruptLoad[PERIODIC_SIZE];
249 tEHCI_QH *LastAsyncHead;
251 Uint32 *PeriodicQueue;
252 tEHCI_QH PeriodicQueueV[PERIODIC_SIZE];
254 tEHCI_QH *QHPools[(256*16)*sizeof(tEHCI_QH)/PAGE_SIZE]; // [PAGE_SIZE/64]
255 tEHCI_qTD *TDPool[PAGE_SIZE/sizeof(tEHCI_qTD)];