4 * - Universal Host Controller Interface
10 typedef struct sUHCI_Controller tUHCI_Controller;
11 typedef struct sUHCI_ExtraTDInfo tUHCI_ExtraTDInfo;
13 typedef struct sUHCI_TD tUHCI_TD;
14 typedef struct sUHCI_QH tUHCI_QH;
17 struct sUHCI_ExtraTDInfo
30 * \brief Next Entry in list
34 * 2 - Depth/Breadth Select
36 * 0 - Terminate (Last in List)
41 * \brief Control and Status Field
44 * 29 - Short Packet Detect (Input Only)
45 * 28:27 - Number of Errors Allowed
46 * 26 - Low Speed Device (Communicating with a low speed device)
47 * 25 - Isynchonious Select
48 * 24 - Interrupt on Completion (IOC)
52 * 21 - Data Buffer Error
53 * 20 - Babble Detected
55 * 18 - CRC/Timout Error
59 * 10:0 - Actual Length (Number of bytes transfered)
64 * \brief Packet Header
66 * 31:21 - Maximum Length (0=1, Max 0x4FF, 0x7FF=0)
70 * 14:8 - Device Address
71 * 7:0 - PID (Packet Identifcation) - Only 96, E1, 2D allowed
80 * \brief Pointer to the data to send
86 tUHCI_ExtraTDInfo *ExtraInfo;
87 char bActive; // Allocated
88 Uint8 QueueIndex; // QH, 0-127 are interrupt, 128 undef, 129 Control, 130 Bulk
89 char bFreePointer; // Free \a BufferPointer once done
91 } __attribute__((aligned(16)));
96 * \brief Next Entry in list
101 * 0 - Terminate (Last in List)
107 * \brief Next Entry in list
112 * 0 - Terminate (Last in List)
117 * \note Area for software use
118 * \brief Last TD in this list, used to add things to the end
121 } __attribute__((aligned(16)));
123 struct sUHCI_Controller
126 * \brief PCI Device ID
131 * \brief IO Base Address
136 * \brief Memory Mapped-IO base address
141 * \brief IRQ Number assigned to the device
146 * \brief Number of the last frame to be cleaned
148 int LastCleanedFrame;
153 * 31:4 - Frame Pointer
156 * 0 - Terminate (Empty Pointer)
161 * \brief Physical Address of the Frame List
163 tPAddr PhysFrameList;
169 // int FrameLoads[1024];
174 // 127 Interrupt Queue Heads
175 // - 4ms -> 256ms range of periods
176 tUHCI_QH InterruptQHs[0];
177 tUHCI_QH InterruptQHs_256ms[64];
178 tUHCI_QH InterruptQHs_128ms[32];
179 tUHCI_QH InterruptQHs_64ms [16];
180 tUHCI_QH InterruptQHs_32ms [ 8];
181 tUHCI_QH InterruptQHs_16ms [ 4];
182 tUHCI_QH InterruptQHs_8ms [ 2];
183 tUHCI_QH InterruptQHs_4ms [ 1];
189 tUHCI_TD LocalTDPool[ (4096-(128+2)*sizeof(tUHCI_QH)) / sizeof(tUHCI_TD) ];
193 // === ENUMERATIONS ===
196 * \brief USB Command Register
199 * 7 - Maximum Packet Size selector (1: 64 bytes, 0: 32 bytes)
200 * 6 - Configure Flag (No Hardware Effect)
201 * 5 - Software Debug (Don't think it will be needed)
202 * 4 - Force Global Resume
203 * 3 - Enter Global Suspend Mode
204 * 2 - Global Reset (Resets all devices on the bus)
205 * 1 - Host Controller Reset (Reset just the controller)
210 * \brief USB Status Register
213 * 5 - HC Halted, set to 1 when USBCMD:RS is set to 0
214 * 4 - Host Controller Process Error (Errors related to the bus)
215 * 3 - Host System Error (Errors related to the OS/PCI Bus)
216 * 2 - Resume Detect (Set if a RESUME command is sent to the Controller)
217 * 1 - USB Error Interrupt
218 * 0 - USB Interrupts (Set if a transaction with the IOC bit set is completed)
222 * \brief USB Interrupt Enable Register
225 * 3 - Short Packet Interrupt Enable
226 * 2 - Interrupt on Complete (IOC) Enable
227 * 1 - Resume Interrupt Enable
228 * 0 - Timout / CRC Error Interrupt Enable
232 * \brief Frame Number (Index into the Frame List)
235 * 10:0 - Index (Incremented each approx 1ms)
239 * \brief Frame List Base Address
241 * 31:12 - Pysical Address >> 12
242 * 11:0 - Reserved (Set to Zero)
244 FLBASEADD = 0x08, // 32-bit
246 * \brief Start-of-frame Modify Register
249 * Sets the size of a frame
250 * Frequency = (11936+n)/12000 kHz
255 SOFMOD = 0x0C, // 8bit
257 * \brief Port Status and Controll Register (Port 1)
263 * 8 - Low Speed Device Attached
265 * 3 - Port Enable/Disable Change - Used for detecting device removal
266 * 2 - Port Enable/Disable
267 * 1 - Connect Status Change
268 * 0 - Current Connect Status
272 * \brief Port Status and Controll Register (Port 2)