4 * - Universal Host Controller Interface
10 typedef struct sUHCI_Controller tUHCI_Controller;
11 typedef struct sUHCI_EndpointInfo tUHCI_EndpointInfo;
12 typedef struct sUHCI_ExtraTDInfo tUHCI_ExtraTDInfo;
14 typedef struct sUHCI_TD tUHCI_TD;
15 typedef struct sUHCI_QH tUHCI_QH;
18 struct sUHCI_ExtraTDInfo
28 struct sUHCI_EndpointInfo
30 unsigned MaxPacketSize : 12;
35 #define TD_CTL_IOC (1 << 24)
36 #define TD_CTL_ACTIVE (1 << 23)
37 #define TD_CTL_STALLED (1 << 22)
38 #define TD_CTL_DATABUFERR (1 << 21)
39 #define TD_CTL_BABBLE (1 << 20)
40 #define TD_CTL_NAK (1 << 19)
41 #define TD_CTL_CRCERR (1 << 18)
42 #define TD_CTL_BITSTUFF (1 << 17)
43 #define TD_CTL_RESERVED (1 << 16)
48 * \brief Next Entry in list
52 * 2 - Depth/Breadth Select
54 * 0 - Terminate (Last in List)
59 * \brief Control and Status Field
62 * 29 - Short Packet Detect (Input Only)
63 * 28:27 - Number of Errors Allowed
64 * 26 - Low Speed Device (Communicating with a low speed device)
65 * 25 - Isynchonious Select
66 * 24 - Interrupt on Completion (IOC)
70 * 21 - Data Buffer Error
71 * 20 - Babble Detected
73 * 18 - CRC/Timout Error
77 * 10:0 - Actual Length (Number of bytes transfered)
82 * \brief Packet Header
84 * 31:21 - Maximum Length (0=1, Max 0x4FF, 0x7FF=0)
88 * 14:8 - Device Address
89 * 7:0 - PID (Packet Identifcation) - Only 96, E1, 2D allowed
98 * \brief Pointer to the data to send
100 Uint32 BufferPointer;
104 tUHCI_ExtraTDInfo *ExtraInfo;
105 char bActive; // Allocated
106 Uint8 QueueIndex; // QH, 0-127 are interrupt, 128 undef, 129 Control, 130 Bulk
107 char bFreePointer; // Free \a BufferPointer once done
109 } __attribute__((aligned(16)));
114 * \brief Next Entry in list
119 * 0 - Terminate (Last in List)
124 * \brief Next Entry in list
129 * 0 - Terminate (Last in List)
134 * \note Area for software use
135 * \brief Last TD in this list, used to add things to the end
138 } __attribute__((aligned(16)));
140 struct sUHCI_Controller
143 * \brief PCI Device ID
148 * \brief IO Base Address
153 * \brief Memory Mapped-IO base address
158 * \brief IRQ Number assigned to the device
163 * \brief Number of the last frame to be cleaned
165 int LastCleanedFrame;
170 * 31:4 - Frame Pointer
173 * 0 - Terminate (Empty Pointer)
178 * \brief Physical Address of the Frame List
180 tPAddr PhysFrameList;
185 * \brief Load in bytes on each interrupt queue
187 int InterruptLoad[128];
192 // 127 Interrupt Queue Heads
193 // - 4ms -> 256ms range of periods
194 tUHCI_QH InterruptQHs[0];
195 tUHCI_QH InterruptQHs_256ms[64];
196 tUHCI_QH InterruptQHs_128ms[32];
197 tUHCI_QH InterruptQHs_64ms [16];
198 tUHCI_QH InterruptQHs_32ms [ 8];
199 tUHCI_QH InterruptQHs_16ms [ 4];
200 tUHCI_QH InterruptQHs_8ms [ 2];
201 tUHCI_QH InterruptQHs_4ms [ 1];
207 tUHCI_TD LocalTDPool[ (4096-(128+2)*sizeof(tUHCI_QH)) / sizeof(tUHCI_TD) ];
211 tUHCI_EndpointInfo EndpointInfo[16];
215 // === ENUMERATIONS ===
218 * \brief USB Command Register
221 * 7 - Maximum Packet Size selector (1: 64 bytes, 0: 32 bytes)
222 * 6 - Configure Flag (No Hardware Effect)
223 * 5 - Software Debug (Don't think it will be needed)
224 * 4 - Force Global Resume
225 * 3 - Enter Global Suspend Mode
226 * 2 - Global Reset (Resets all devices on the bus)
227 * 1 - Host Controller Reset (Reset just the controller)
232 * \brief USB Status Register
235 * 5 - HC Halted, set to 1 when USBCMD:RS is set to 0
236 * 4 - Host Controller Process Error (Errors related to the bus)
237 * 3 - Host System Error (Errors related to the OS/PCI Bus)
238 * 2 - Resume Detect (Set if a RESUME command is sent to the Controller)
239 * 1 - USB Error Interrupt
240 * 0 - USB Interrupts (Set if a transaction with the IOC bit set is completed)
244 * \brief USB Interrupt Enable Register
247 * 3 - Short Packet Interrupt Enable
248 * 2 - Interrupt on Complete (IOC) Enable
249 * 1 - Resume Interrupt Enable
250 * 0 - Timout / CRC Error Interrupt Enable
254 * \brief Frame Number (Index into the Frame List)
257 * 10:0 - Index (Incremented each approx 1ms)
261 * \brief Frame List Base Address
263 * 31:12 - Pysical Address >> 12
264 * 11:0 - Reserved (Set to Zero)
266 FLBASEADD = 0x08, // 32-bit
268 * \brief Start-of-frame Modify Register
271 * Sets the size of a frame
272 * Frequency = (11936+n)/12000 kHz
277 SOFMOD = 0x0C, // 8bit
279 * \brief Port Status and Controll Register (Port 1)
285 * 8 - Low Speed Device Attached
287 * 3 - Port Enable/Disable Change - Used for detecting device removal
288 * 2 - Port Enable/Disable
289 * 1 - Connect Status Change
290 * 0 - Current Connect Status
294 * \brief Port Status and Controll Register (Port 2)