3 * - By John Hodge (thePowersGang)
18 extern void *gpIRQHandler;
19 extern tPAddr gGIC_DistributorAddr;
20 extern tPAddr gGIC_InterfaceAddr;
23 typedef void (*tIRQ_Handler)(int, void*);
26 int GIC_Install(char **Arguments);
27 void GIC_IRQHandler(void);
30 MODULE_DEFINE(0, 0x100, armv7_GIC, GIC_Install, NULL, NULL);
31 volatile Uint32 *gpGIC_DistributorBase;
32 volatile Uint32 *gpGIC_InterfaceBase;
33 tIRQ_Handler gaIRQ_Handlers[N_IRQS];
34 void *gaIRQ_HandlerData[N_IRQS];
37 int GIC_Install(char **Arguments)
40 Log_Debug("GIC", "Dist: %P, Interface: %P",
41 gGIC_DistributorAddr, gGIC_InterfaceAddr);
42 gpGIC_InterfaceBase = (Uint32*)MM_MapHWPages(gGIC_InterfaceAddr, 1)
43 + (gGIC_InterfaceAddr & (PAGE_SIZE-1))/4;
44 gpGIC_DistributorBase = (void*)MM_MapHWPages(gGIC_DistributorAddr, 1);
46 gpGIC_InterfaceBase[GICC_CTLR] = 0; // Disable CPU interaface
47 gpGIC_InterfaceBase[GICC_PMR] = 0xFF; // Effectively disable prioritories
48 gpGIC_InterfaceBase[GICC_CTLR] = 1; // Enable CPU
49 gpGIC_DistributorBase[GICD_CTLR] = 1; // Enable Distributor
51 gpIRQHandler = GIC_IRQHandler;
53 __asm__ __volatile__ ("cpsie if"); // Enable IRQs and FIQs
56 for( int i = 0; i < N_IRQS/32; i ++ ) {
57 Log_Debug("GIC", "GICD_ISENABLER%i %x = %08x",
58 i, GICD_ISENABLER0 + i,
59 gpGIC_DistributorBase[GICD_ISENABLER0+i]);
60 gpGIC_DistributorBase[GICD_ISENABLER0+i] = 0;
65 // Testing - First 32 actual interrupts enabled
66 gpGIC_DistributorBase[GICD_ISENABLER0+1] = 0xFFFFFFFF;
67 for( int i = 0; i < 32/4; i ++ )
68 gpGIC_DistributorBase[GICD_ITARGETSR0+8+i] = 0x01010101;
71 // Clear out pending IRQs.
72 gpGIC_InterfaceBase[GICC_EOIR] = gpGIC_InterfaceBase[GICC_IAR];
77 void GIC_IRQHandler(void)
79 Uint32 num = gpGIC_InterfaceBase[GICC_IAR];
80 if( gaIRQ_Handlers[num] ) {
81 gaIRQ_Handlers[num]( num, gaIRQ_HandlerData[num] );
84 Log_Debug("GIC", "IRQ 0x%x unhandled", num);
86 gpGIC_InterfaceBase[GICC_EOIR] = num;
89 int IRQ_AddHandler(int IRQ, tIRQ_Handler Handler, void *Ptr)
91 if( IRQ < 0 || IRQ >= N_IRQS-32 ) {
95 IRQ += 32; // 32 internal IRQs
96 // - Enable IRQ, clear pending and send to CPU 1 only
97 gpGIC_DistributorBase[GICD_ISENABLER0+IRQ/32] = 1 << (IRQ & (32-1));
98 ((Uint8*)&gpGIC_DistributorBase[GICD_ITARGETSR0])[IRQ] = 1;
99 gpGIC_DistributorBase[GICD_ICPENDR0+IRQ/32] = 1 << (IRQ & (32-1));
100 gpGIC_DistributorBase[GICD_ICFGR0+IRQ/16] |= 2 << ((IRQ & 15)*2);
102 // TODO: Does the GIC need to handle IRQ sharing?
103 if( gaIRQ_Handlers[IRQ] ) {
104 Log_Warning("GIC", "IRQ %i already handled by %p, %p ignored",
105 IRQ, gaIRQ_Handlers[IRQ], Handler);
109 gaIRQ_Handlers[IRQ] = Handler;
110 gaIRQ_HandlerData[IRQ] = Ptr;
112 Log_Debug("GIC", "IRQ %i handled by %p(%p)", IRQ, Handler, Ptr);