KernelLand/Modules/armv7/GIC/gic.h

   1 /*
   2  * ARMv7 GIC Support
   3  * - By John Hodge (thePowersGang)
   4  *
   5  * gic.h
   6  * - GIC Core Definitions
   7  */
   8 #ifndef _ARM7_GIC_H_
   9 #define _ARM7_GIC_H_
  10
  11 enum eGICD_Registers
  12 {
  13         GICD_CTLR       = 0x000/4,      // Distributor Control Register
  14         GICD_TYPER      = 0x004/4,      // Interrupt Controller Type
  15         GICD_IIDR       = 0x008/4,      // Distributor Implementer Identifcation
  16
  17         GICD_IGROUPR0   = 0x080/4,      // Interrupt Group Register (#0)
  18         GICD_ISENABLER0 = 0x100/4,      // Interrupt Set-Enable Register #0 (128*8=1024)
  19         GICD_ICENABLER0 = 0x180/4,      // Interrupt Clear-Enable Register #0
  20         GICD_ISPENDR0   = 0x200/4,      // Interrupt Set-Pending Register #0
  21         GICD_ICPENDR0   = 0x280/4,      // Interrupt Clear-Pending Register #0
  22         GICD_ISACTIVER0 = 0x300/4,      // Interrupt Set-Active Register (GICv2)
  23         GICD_ICACTIVER0 = 0x380/4,      // Interrupt Clear-Active Register (GICv2)
  24
  25         GICD_IPRIORITYR0 = 0x400/4,     // Interrupt priority registers (254*4 = )
  26
  27         GICD_ITARGETSR0 = 0x800/4,      // Interrupt Processor Targets Register (8*4)
  28
  29         GICD_ICFGR0     = 0xC00/4,      // Interrupt Configuration Register (64*4)
  30         GICD_NSACR0     = 0xE00/4,      // Non-secure Access Control Register (64*4)
  31         GICD_SIGR       = 0xF00/4,      // Software Generated Interrupt Register (Write Only)
  32         GICD_CPENDSGIR0 = 0xF10/4,      // SGI Clear-Pending Registers (4*4)
  33         GICD_SPENDSGIR0 = 0xF20/4,      // SGI Set-Pending Registers (4*4)
  34 };
  35
  36 enum eGICC_Registers
  37 {
  38         GICC_CTLR   = 0x000/4,  // CPU Interface Control Register
  39         GICC_PMR    = 0x004/4,  // Interrupt Priority Mask Register
  40         GICC_BPR    = 0x008/4,  // Binary Point Register
  41         GICC_IAR    = 0x00C/4,  // Interrupt Acknowledge Register
  42         GICC_EOIR   = 0x010/4,  // End of Interrupt Register
  43         GICC_RPR    = 0x014/4,  // Running Priority Register
  44         GICC_HPPIR  = 0x018/4,  // Highest Priority Pending Interrupt Register
  45         GICC_ABPR   = 0x01C/4,  // Aliased Binary Point Register
  46         GICC_AIAR   = 0x020/4,  // Aliased Interrupt Acknowledge Register,
  47         GICC_AEOIR  = 0x024/4,  // Aliased End of Interrupt Register
  48         GICC_AHPPIR = 0x028/4,  // Aliased Highest Priority Pending Interrupt Register
  49
  50         GICC_APR0   = 0x0D0/4,  // Active Priorities Registers (4*4)
  51         GICC_NSAPR0 = 0x0E0/4,  // Non-secure Active Priorities Registers (4*4)
  52
  53         GICC_IIDR   = 0x0FC/4,  // CPU Interface Identifcation Register
  54         GICC_DIR    = 0x0FC/4,  // Deactivate Interrupt Register (Write Only)
  55 };
  56
  57 #endif