2 * Acess2 NVidia Tegra2 Display Driver
3 * - By John Hodge (thePowersGang)
8 #ifndef _TEGRA2_DISP_H_
9 #define _TEGRA2_DISP_H_
11 #define TEGRA2VID_BASE 0x54200000 // 0x40000 Large (256 KB)
13 const struct sTegra2_Disp_Mode
19 } caTegra2Vid_Modes[] = {
21 {720, 487, 16,33, 63, 33, 59, 133}, // NTSC 2
22 {720, 576, 12,33, 63, 33, 69, 193}, // PAL 2 (VFP shown as 2/33, used 33)
23 {720, 483, 16, 6, 63, 6, 59, 30}, // 480p
24 {1280, 720, 70, 5, 804, 6, 220, 20}, // 720p
25 {1920,1080, 44, 4, 884, 5, 148, 36}, // 1080p
26 // TODO: Can all but HA/VA be constant and those select the resolution?
28 const int ciTegra2Vid_ModeCount = sizeof(caTegra2Vid_Modes)/sizeof(caTegra2Vid_Modes[0]);
30 enum eTegra2_Disp_Regs
32 DC_DISP_DISP_SIGNAL_OPTIONS0_0 = 0x400,
33 DC_DISP_DISP_SIGNAL_OPTIONS1_0,
34 DC_DISP_DISP_WIN_OPTIONS_0,
35 DC_DISP_MEM_HIGH_PRIORITY_0,
36 DC_DISP_MEM_HIGH_PRIORITY_TIMER_0,
37 DC_DISP_DISP_TIMING_OPTIONS_0,
38 DC_DISP_REF_TO_SYNC_0,
41 DC_DISP_DISP_ACTIVE_0,
42 DC_DISP_FRONT_PORCH_0,
44 DC_DISP_H_PULSE0_CONTROL_0,
46 DC_DISP_DISP_COLOR_CONTROL_0 = 0x430,
48 DC_WINC_A_COLOR_PALETTE_0 = 0x500,
49 DC_WINC_A_PALETTE_COLOR_EXT_0 = 0x600,
50 DC_WIN_A_WIN_OPTIONS_0 = 0x700,
52 DC_WIN_A_BUFFER_CONTROL_0,
53 DC_WIN_A_COLOR_DEPTH_0,
56 DC_WIN_A_PRESCALED_SIZE_0,
57 DC_WIN_A_H_INITIAL_DDA_0,
58 DC_WIN_A_V_INITIAL_DDA_0,
59 DC_WIN_A_DDA_INCREMENT_0,
60 DC_WIN_A_LINE_STRIDE_0,
61 DC_WIN_A_BUF_STRIDE_0,
62 DC_WIN_A_BUFFER_ADDR_MODE_0,
63 DC_WIN_A_DV_CONTROL_0,
64 DC_WIN_A_BLEND_NOKEY_0,
66 DC_WINBUF_A_START_ADDR_0 = 0x800,
67 DC_WINBUF_A_START_ADDR_NS_0,
68 DC_WINBUF_A_ADDR_H_OFFSET_0,
69 DC_WINBUF_A_ADDR_H_OFFSET_NS_0,
70 DC_WINBUF_A_ADDR_V_OFFSET_0,
71 DC_WINBUF_A_ADDR_V_OFFSET_NS_0,