3 * Universal Host Controller Interface
13 #define MAX_CONTROLLERS 4
17 int UHCI_Initialise();
19 tUHCI_TD *UHCI_int_AllocateTD(tUHCI_Controller *Cont);
20 void UHCI_int_AppendTD(tUHCI_Controller *Cont, tUHCI_TD *TD);
21 int UHCI_int_SendTransaction(tUHCI_Controller *Cont, int Fcn, int Endpt, int DataTgl, Uint8 Type, void *Data, size_t Length);
22 int UHCI_DataIN(void *Ptr, int Fcn, int Endpt, int DataTgl, void *Data, size_t Length);
23 int UHCI_DataOUT(void *Ptr, int Fcn, int Endpt, int DataTgl, void *Data, size_t Length);
24 int UHCI_SendSetup(void *Ptr, int Fcn, int Endpt, int DataTgl, void *Data, size_t Length);
25 int UHCI_Int_InitHost(tUHCI_Controller *Host);
26 void UHCI_InterruptHandler(int IRQ, void *Ptr);
29 tUHCI_TD gaUHCI_TDPool[NUM_TDs];
30 tUHCI_Controller gUHCI_Controllers[MAX_CONTROLLERS];
31 tUSBHost gUHCI_HostDef = {
32 .SendIN = UHCI_DataIN,
33 .SendOUT = UHCI_DataOUT,
34 .SendSETUP = UHCI_SendSetup,
39 * \fn int UHCI_Initialise()
40 * \brief Called to initialise the UHCI Driver
42 int UHCI_Initialise(const char **Arguments)
49 // Enumerate PCI Bus, getting a maximum of `MAX_CONTROLLERS` devices
50 while( (id = PCI_GetDeviceByClass(0x0C03, 0xFFFF, id)) >= 0 && i < MAX_CONTROLLERS )
52 tUHCI_Controller *cinfo = &gUHCI_Controllers[i];
53 // NOTE: Check "protocol" from PCI?
56 // Assign a port range (BAR4, Reserve 32 ports)
57 cinfo->IOBase = PCI_GetBAR(id, 4);
58 if( !(cinfo->IOBase & 1) ) {
59 Log_Warning("UHCI", "MMIO is not supported");
62 cinfo->IRQNum = PCI_GetIRQ(id);
64 Log_Debug("UHCI", "Controller PCI #%i: IO Base = 0x%x, IRQ %i",
65 id, cinfo->IOBase, cinfo->IRQNum);
67 IRQ_AddHandler(cinfo->IRQNum, UHCI_InterruptHandler, cinfo);
70 ret = UHCI_Int_InitHost(&gUHCI_Controllers[i]);
77 USB_RegisterHost(&gUHCI_HostDef, cinfo);
81 if(i == MAX_CONTROLLERS) {
82 Log_Warning("UHCI", "Over "EXPAND_STR(MAX_CONTROLLERS)" UHCI controllers detected, ignoring rest");
89 * \fn void UHCI_Cleanup()
90 * \brief Called just before module is unloaded
96 tUHCI_TD *UHCI_int_AllocateTD(tUHCI_Controller *Cont)
99 for(i = 0; i < NUM_TDs; i ++)
101 if(gaUHCI_TDPool[i].Link == 0) {
102 gaUHCI_TDPool[i].Link = 1;
103 return &gaUHCI_TDPool[i];
109 void UHCI_int_AppendTD(tUHCI_Controller *Cont, tUHCI_TD *TD)
115 * \brief Send a transaction to the USB bus
116 * \param ControllerID Controller
117 * \param Fcn Function Address
118 * \param Endpt Endpoint
120 int UHCI_int_SendTransaction(tUHCI_Controller *Cont, int Fcn, int Endpt, int DataTgl, Uint8 Type, void *Data, size_t Length)
124 if( Length > 0x400 ) return -1; // Controller allows up to 0x500, but USB doesn't
126 td = UHCI_int_AllocateTD(Cont);
129 td->Control = (Length - 1) & 0x7FF;
130 td->Token = ((Length - 1) & 0x7FF) << 21;
131 td->Token |= (DataTgl & 1) << 19;
132 td->Token |= (Endpt & 0xF) << 15;
133 td->Token |= (Fcn & 0xFF) << 8;
136 // TODO: Ensure 32-bit paddr
137 if( ((tVAddr)Data & PAGE_SIZE) + Length > PAGE_SIZE ) {
138 Log_Warning("UHCI", "TODO: Support non single page transfers");
139 // td->BufferPointer =
143 td->BufferPointer = MM_GetPhysAddr( (tVAddr)Data );
146 UHCI_int_AppendTD(Cont, td);
148 // Wait until done, then return
154 int UHCI_DataIN(void *Ptr, int Fcn, int Endpt, int DataTgl, void *Data, size_t Length)
156 return UHCI_int_SendTransaction(Ptr, Fcn, Endpt, DataTgl, 0x69, Data, Length);
159 int UHCI_DataOUT(void *Ptr, int Fcn, int Endpt, int DataTgl, void *Data, size_t Length)
161 return UHCI_int_SendTransaction(Ptr, Fcn, Endpt, DataTgl, 0xE1, Data, Length);
164 int UHCI_SendSetup(void *Ptr, int Fcn, int Endpt, int DataTgl, void *Data, size_t Length)
166 return UHCI_int_SendTransaction(Ptr, Fcn, Endpt, DataTgl, 0x2D, Data, Length);
169 // === INTERNAL FUNCTIONS ===
171 * \fn int UHCI_Int_InitHost(tUCHI_Controller *Host)
172 * \brief Initialises a UHCI host controller
173 * \param Host Pointer - Host to initialise
175 int UHCI_Int_InitHost(tUHCI_Controller *Host)
177 ENTER("pHost", Host);
179 outw( Host->IOBase + USBCMD, 4 ); // GRESET
180 // TODO: Wait for at least 10ms
181 outw( Host->IOBase + USBCMD, 0 ); // GRESET
183 // Allocate Frame List
184 // - 1 Page, 32-bit address
185 // - 1 page = 1024 4 byte entries
186 Host->FrameList = (void *) MM_AllocDMA(1, 32, &Host->PhysFrameList);
187 if( !Host->FrameList ) {
188 Log_Warning("UHCI", "Unable to allocate frame list, aborting");
192 LOG("Allocated frame list 0x%x (0x%x)", Host->FrameList, Host->PhysFrameList);
193 memsetd( Host->FrameList, 1, 1024 ); // Clear List (Disabling all entries)
195 //! \todo Properly fill frame list
197 // Set frame length to 1 ms
198 outb( Host->IOBase + SOFMOD, 64 );
200 // Set Frame List Address
201 outd( Host->IOBase + FLBASEADD, Host->PhysFrameList );
204 outw( Host->IOBase + FRNUM, 0 );
207 // PCI_WriteWord( Host->PciId, 0xC0, 0x2000 );
213 void UHCI_InterruptHandler(int IRQ, void *Ptr)